X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=cfg%2Fcpu.h;h=f845bde1239daa0530e90708af6ca141c4096909;hb=60336b428df2d4a973b79b23cd41ce48f7043b5b;hp=a687275fc095f7f641a180b63ddb544a337951c1;hpb=aa123fd1e115e8b7c3d9e9b6ac2e59e1741c9313;p=bertos.git

diff --git a/cfg/cpu.h b/cfg/cpu.h
index a687275f..f845bde1 100755
--- a/cfg/cpu.h
+++ b/cfg/cpu.h
@@ -17,6 +17,24 @@
 
 /*#*
  *#* $Log$
+ *#* Revision 1.12  2006/03/21 10:52:39  bernie
+ *#* Update ARM support.
+ *#*
+ *#* Revision 1.11  2006/03/20 17:49:00  bernie
+ *#* Spacing fix.
+ *#*
+ *#* Revision 1.10  2006/02/24 01:17:30  bernie
+ *#* CPU_SAVED_REGS_CNT: Declare for x86/x86_64.
+ *#*
+ *#* Revision 1.9  2006/02/23 09:08:43  bernie
+ *#* Add note for a frequently reported non-bug.
+ *#*
+ *#* Revision 1.8  2006/02/10 12:37:45  bernie
+ *#* Add support for ARM on IAR.
+ *#*
+ *#* Revision 1.7  2005/11/27 03:04:38  bernie
+ *#* Add POSIX emulation for IRQ_* macros; Add Qt support.
+ *#*
  *#* Revision 1.6  2005/07/19 07:26:49  bernie
  *#* Add missing #endif.
  *#*
@@ -64,7 +82,7 @@
  * \{
  */
 #define CPU_BIG_ENDIAN    0x1234
-#define CPU_LITTLE_ENDIAN 0x3412
+#define CPU_LITTLE_ENDIAN 0x3412 /* Look twice, pal. This is not a bug. */
 /*\}*/
 
 /*! Macro to include cpu-specific versions of the headers. */
@@ -93,14 +111,20 @@
 #elif CPU_X86
 
 	#define NOP                     asm volatile ("nop")
-	#define IRQ_DISABLE             FIXME
-	#define IRQ_ENABLE              FIXME
-	#define IRQ_SAVE_DISABLE(x)     FIXME
-	#define IRQ_RESTORE(x)          FIXME
 
-	typedef uint32_t cpuflags_t; // FIXME
+	/* Get IRQ_* definitions from the hosting environment. */
+	#include <cfg/os.h>
+	#if OS_EMBEDDED
+		#define IRQ_DISABLE             FIXME
+		#define IRQ_ENABLE              FIXME
+		#define IRQ_SAVE_DISABLE(x)     FIXME
+		#define IRQ_RESTORE(x)          FIXME
+		typedef uint32_t cpuflags_t; // FIXME
+	#endif /* OS_EMBEDDED */
+
 
 	#define CPU_REGS_CNT            7
+	#define CPU_SAVED_REGS_CNT      7
 	#define CPU_STACK_GROWS_UPWARD  0
 	#define CPU_SP_ON_EMPTY_SLOT	0
 	#define CPU_BYTE_ORDER          CPU_LITTLE_ENDIAN
@@ -119,8 +143,121 @@
 		#define CPU_REG_BITS    32
 	#endif
 
+#elif CPU_ARM
+
+	typedef uint32_t cpuflags_t;
+	typedef uint32_t cpustack_t;
+
+	/* Register counts include SREG too */
+	#define CPU_REG_BITS           32
+	#define CPU_REGS_CNT           16
+	#define CPU_SAVED_REGS_CNT     FIXME
+	#define CPU_STACK_GROWS_UPWARD 0  //FIXME
+	#define CPU_SP_ON_EMPTY_SLOT   0  //FIXME
+	#define CPU_BYTE_ORDER         (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN)
+	#define CPU_HARVARD            0
+
+	#ifdef __IAR_SYSTEMS_ICC__
+
+		#include <inarm.h>
+
+		#if __CPU_MODE__ == 1 /* Thumb */
+			/* Use stubs */
+			extern cpuflags_t get_CPSR(void);
+			extern void set_CPSR(cpuflags_t flags);
+		#else
+			#define get_CPSR __get_CPSR
+			#define set_CPSR __set_CPSR
+		#endif
+
+		#define NOP         __no_operation()
+		#define IRQ_DISABLE __disable_interrupt()
+		#define IRQ_ENABLE  __enable_interrupt()
+
+		#define IRQ_SAVE_DISABLE(x) \
+		do { \
+			(x) = get_CPSR(); \
+			__disable_interrupt(); \
+		} while (0)
+
+		#define IRQ_RESTORE(x) \
+		do { \
+			set_CPSR(x); \
+		} while (0)
+
+		#define IRQ_GETSTATE() \
+			((bool)(get_CPSR() & 0xb0))
+
+		#define BREAKPOINT  /* asm("bkpt 0") DOES NOT WORK */
+
+	#else /* !__IAR_SYSTEMS_ICC__ */
+
+		#warning "IRQ_ macros need testing!"
+
+		#define NOP         asm volatile ("mov r0,r0" ::)
+
+		#define IRQ_DISABLE \
+		do { \
+			asm volatile ( \
+				"mrs r0, cpsr\n\t" \
+				"orr r0, r0, #0xb0\n\t" \
+				"msr cpsr, r0" \
+				:: \
+			); \
+		} while (0)
+
+		#define IRQ_ENABLE \
+		do { \
+			asm volatile ( \
+				"mrs r0, cpsr\n\t" \
+				"bic r0, r0, #0xb0\n\t" \
+				"msr cpsr, r0" \
+				:: \
+			); \
+		} while (0)
+
+		#define IRQ_SAVE_DISABLE(x) \
+		do { \
+			asm volatile ( \
+				"mrs r0, cpsr\n\t" \
+				"mov %0, r0\n\t" \
+				"orr r0, r0, #0xb0\n\t" \
+				"msr cpsr, r0" \
+				: "=r" (x) \
+				: /* no inputs */ \
+				: "r0" \
+			); \
+		} while (0)
+
+		#define IRQ_RESTORE(x) \
+		do { \
+			asm volatile ( \
+				"mov r0, %0\n\t" \
+				"msr cpsr, r0" \
+				: /* no outputs */ \
+				: "r" (x) \
+				: "r0" \
+			); \
+		} while (0)
+
+		#define IRQ_GETSTATE() \
+		({ \
+			uint32_t sreg; \
+			asm volatile ( \
+				"mrs r0, cpsr\n\t" \
+				"mov %0, r0" \
+				: "=r" (sreg)
+				: /* no inputs */
+				: "r0" \
+			); \
+			(bool)(sreg & 0xb0); \
+		})
+
+	#endif /* __IAR_SYSTEMS_ICC_ */
+
 #elif CPU_PPC
 	#define NOP                 asm volatile ("nop" ::)
+
 	#define IRQ_DISABLE         FIXME
 	#define IRQ_ENABLE          FIXME
 	#define IRQ_SAVE_DISABLE(x) FIXME
@@ -330,7 +467,7 @@
 
 #else
 	#define CPU_PUSH_CALL_CONTEXT(sp, func) \
-		CPU_PUSH_WORD((sp), (func))
+		CPU_PUSH_WORD((sp), (cpustack_t)(func))
 #endif