X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=cpu%2Farm%2Fdrv%2Fser_at91.c;h=30bd049ce48e2188f72d128a09172925081ef42e;hb=3110ae0831fa4ba081c9206663390e21c7a4f78a;hp=a35a90c7e3c65c0477398df94781b4e63461c9e5;hpb=96bda3a8889719af5e4475aaf853487f2e99e01f;p=bertos.git

diff --git a/cpu/arm/drv/ser_at91.c b/cpu/arm/drv/ser_at91.c
index a35a90c7..30bd049c 100644
--- a/cpu/arm/drv/ser_at91.c
+++ b/cpu/arm/drv/ser_at91.c
@@ -74,7 +74,87 @@
  * \{
  */
 
+#ifndef SER_UART0_IRQ_INIT
+	/**
+	 * Default IRQ INIT macro - invoked in uart0_init()
+	 *
+	 * - Disable all interrupt
+	 * - Register USART0 interrupt
+	 * - Enable USART0 clock.
+	 */
+	#define SER_UART0_IRQ_INIT do { \
+		US0_IDR = 0xFFFFFFFF; \
+		/* Set the vector. */ \
+		AIC_SVR(US0_ID) = uart0_irq_dispatcher; \
+		/* Initialize to edge triggered with defined priority. */ \
+		AIC_SMR(US0_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED; \
+		/* Enable the USART IRQ */ \
+		AIC_IECR = BV(US0_ID); \
+		PMC_PCER = BV(US0_ID); \
+	} while (0)
+#endif
+
+#ifndef SER_UART0_BUS_TXINIT
+	/**
+	 * Default TXINIT macro - invoked in uart0_init()
+	 *
+	 * - Disable GPIO on USART0 tx/rx pins
+	 * - Reset USART0
+	 * - Set serial param: mode Normal, 8bit data, 1bit stop
+	 * - Enable both the receiver and the transmitter
+	 * - Enable only the RX complete interrupt
+	 */
+	#if CPU_ARM_AT91
+		#define SER_UART0_BUS_TXINIT do { \
+			PIOA_PDR = BV(5) | BV(6);\
+			US0_CR = BV(US_RSTRX) | BV(US_RSTTX); \
+			US0_MR = US_CHMODE_NORMAL | US_CHRL_8 | US_NBSTOP_1; \
+			US0_CR = BV(US_RXEN) | BV(US_TXEN); \
+			US0_IER = BV(US_RXRDY); \
+		} while (0)
+	/*#elif  Add other ARM families here */
+	#else
+		#error Unknown CPU
+	#endif
+
+#endif
+
+#ifndef SER_UART0_BUS_TXBEGIN
+	/**
+	 * Invoked before starting a transmission
+	 *
+	 * - Enable both the receiver and the transmitter
+	 * - Enable both the RX complete and TX empty interrupts
+	 */
+	#define SER_UART0_BUS_TXBEGIN do { \
+		US0_CR = BV(US_RXEN) | BV(US_TXEN); \
+		US0_IER = BV(US_TXRDY) | BV(US_RXRDY); \
+	} while (0)
+#endif
+
+#ifndef SER_UART0_BUS_TXCHAR
+	/**
+	 * Invoked to send one character.
+	 */
+	#define SER_UART0_BUS_TXCHAR(c) do { \
+		US0_THR = c; \
+	} while (0)
+#endif
 
+#ifndef SER_UART0_BUS_TXEND
+	/**
+	 * Invoked as soon as the txfifo becomes empty
+	 *
+	 * - Keep both the receiver and the transmitter enabled
+	 * - Keep the RX complete interrupt enabled
+	 * - Disable the TX empty interrupts
+	 */
+	#define SER_UART0_BUS_TXEND do { \
+		US0_CR = BV(US_RXEN) | BV(US_TXEN); \
+		US0_IER = BV(US_RXRDY); \
+		US0_IDR = BV(US_TXRDY); \
+	} while (0)
+#endif
 
 /**
  * \def CONFIG_SER_STROBE
@@ -143,14 +223,13 @@ static void serirq_tx(void)
 
 	if (fifo_isempty(txfifo))
 	{
-		/* Enable Tx and Rx */
-		US0_CR = BV(US_RXEN) | BV(US_TXEN);
+		SER_UART0_BUS_TXEND;
 	}
 	else
 	{
 		char c = fifo_pop(txfifo);
-		/* Send one char */
-		US0_THR = c;
+// 		kprintf("Tx char: %c\n", c);
+		SER_UART0_BUS_TXCHAR(c);
 	}
 
 	SER_STROBE_OFF;
@@ -163,7 +242,7 @@ static void serirq_rx(void)
 {
 	SER_STROBE_ON;
 
-	/* Should be read before UDR */
+	/* Should be read before US_CRS */
 	ser_uart0->status |= US0_CSR & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
 
 	char c = US0_RHR;
@@ -173,6 +252,7 @@ static void serirq_rx(void)
 		ser_uart0->status |= SERRF_RXFIFOOVERRUN;
 	else
 	{
+// 		kprintf("Recv char: %c\n", c);
 		fifo_push(rxfifo, c);
 	}
 
@@ -182,17 +262,21 @@ static void serirq_rx(void)
 /**
  * Serial IRQ dispatcher.
  */
-static void serirq_dispatcher(void) __attribute__ ((naked));
-static void serirq_dispatcher(void)
+static void uart0_irq_dispatcher(void) __attribute__ ((naked));
+static void uart0_irq_dispatcher(void)
 {
 	IRQ_ENTRY();
 
-	if (US0_IMR | BV(US_RXRDY))
+	if (US0_IMR & BV(US_RXRDY))
+	{
+//		kprintf("IRQ RX\n");
 		serirq_rx();
-
-	if (US0_IMR | BV(US_TXRDY))
+	}
+	if (US0_IMR & BV(US_TXRDY))
+	{
+//		kprintf("IRQ TX\n");
 		serirq_tx();
-
+	}
 	IRQ_EXIT();
 }
 
@@ -203,35 +287,9 @@ static void uart0_init(
 	UNUSED_ARG(struct SerialHardware *, _hw),
 	UNUSED_ARG(struct Serial *, ser))
 {
-
-	/* Set the vector. */
-	AIC_SVR(US0_ID) = serirq_dispatcher;
-	/* Initialize to edge triggered with defined priority. */
-	AIC_SMR(US0_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED;
-	/* Clear pending interrupt */
-	AIC_ICCR = BV(US0_ID);
-	/* Enable the system IRQ */
-	AIC_IECR = BV(US0_ID);
-
-    /* Enable UART clock. */
-	PMC_PCER = BV(US0_ID);
-
-    /* Disable GPIO on UART tx/rx pins. */
-	PIOA_PDR = BV(PA0_RXD0_A) | BV(PA1_TXD0_A);
-
-	/* Reset UART. */
-	US0_CR = BV(US_RSTRX) | BV(US_RSTTX);
-
-	/* Enable Tx and Rx */
-	US0_CR = BV(US_RXEN) | BV(US_TXEN);
-
-	US0_IER = BV(US_RXRDY);
-
-    /* enable GPIO on UART tx/rx pins. */
-	PIOA_PER = BV(PA0_RXD0_A) | BV(PA1_TXD0_A);
-
-	/* Set serial param: mode Normal, 8bit data, 1bit stop */
-	US0_MR |= US_CHMODE_NORMAL | US_CHRL_8 | US_NBSTOP_1;
+	SER_UART0_IRQ_INIT;
+	SER_UART0_BUS_TXINIT;
+	SER_STROBE_INIT;
 }
 
 static void uart0_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
@@ -251,8 +309,7 @@ static void uart0_enabletxirq(struct SerialHardware *_hw)
 	if (!hw->sending)
 	{
 		hw->sending = true;
-		/* Enable Tx and Rx */
-		US0_CR = BV(US_RXEN) | BV(US_TXEN);
+		SER_UART0_BUS_TXBEGIN;
 	}
 }
 
@@ -332,3 +389,9 @@ static struct ArmSerial UARTDescs[SER_CNT] =
 		C99INIT(sending, false),
 	}
 };
+
+struct SerialHardware *ser_hw_getdesc(int unit)
+{
+	ASSERT(unit < SER_CNT);
+	return &UARTDescs[unit].hw;
+}