X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=cpu%2Farm%2Fdrv%2Fser_at91.c;h=82320bdf1ad1edc699258faa37af2cc678c1773f;hb=139052d58a99cc47e0e2ac6b897a0c26a0105c2a;hp=3069f543e5ae63fb670b75c4aaa8ebe152854125;hpb=d526bd236e1ab66064df24d74c6550f7f8b7fa9a;p=bertos.git diff --git a/cpu/arm/drv/ser_at91.c b/cpu/arm/drv/ser_at91.c index 3069f543..82320bdf 100644 --- a/cpu/arm/drv/ser_at91.c +++ b/cpu/arm/drv/ser_at91.c @@ -34,61 +34,25 @@ * \brief ARM UART and SPI I/O driver * * - * \version $Id: ser_amr.c 18280 2007-10-11 15:14:20Z asterix $ + * \version $Id: ser_at91.c 20881 2008-03-04 14:07:02Z batt $ * \author Daniele Basile */ -#include +#include -//#include "ser_at91.h" +#include #include #include #include /* Required for bus macros overrides */ #include /* CLOCK_FREQ */ -#include #include - #include -#include - -//TODO -#if !CONFIG_SER_HWHANDSHAKE - /** - * \name Hardware handshake (RTS/CTS). - * \{ - */ - #define RTS_ON do {} while (0) - #define RTS_OFF do {} while (0) - #define IS_CTS_ON true - #define EIMSKF_CTS 0 /**< Dummy value, must be overridden */ - /*\}*/ -#endif - -#if CPU_AVR_ATMEGA1281 - #define BIT_RXCIE0 RXCIE0 - #define BIT_RXEN0 RXEN0 - #define BIT_TXEN0 TXEN0 - #define BIT_UDRIE0 UDRIE0 - - #define BIT_RXCIE1 RXCIE1 - #define BIT_RXEN1 RXEN1 - #define BIT_TXEN1 TXEN1 - #define BIT_UDRIE1 UDRIE1 -#else - #define BIT_RXCIE0 RXCIE - #define BIT_RXEN0 RXEN - #define BIT_TXEN0 TXEN - #define BIT_UDRIE0 UDRIE - - #define BIT_RXCIE1 RXCIE - #define BIT_RXEN1 RXEN - #define BIT_TXEN1 TXEN - #define BIT_UDRIE1 UDRIE -#endif +#include +#define SERIRQ_PRIORITY 4 ///< default priority for serial irqs. /** * \name Overridable serial bus hooks @@ -110,28 +74,27 @@ * * \{ */ + #ifndef SER_UART0_BUS_TXINIT /** * Default TXINIT macro - invoked in uart0_init() * - * - Enable both the receiver and the transmitter - * - Enable only the RX complete interrupt + * - Disable GPIO on USART0 tx/rx pins */ + #if !CPU_ARM_AT91SAM7S256 && !CPU_ARM_AT91SAM7X256 && !CPU_ARM_AT91SAM7X128 + #warning Check USART0 pins! + #endif #define SER_UART0_BUS_TXINIT do { \ - UCSR0B = BV(BIT_RXCIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0); \ + PIOA_PDR = BV(RXD0) | BV(TXD0); \ } while (0) + #endif #ifndef SER_UART0_BUS_TXBEGIN /** * Invoked before starting a transmission - * - * - Enable both the receiver and the transmitter - * - Enable both the RX complete and UDR empty interrupts */ - #define SER_UART0_BUS_TXBEGIN do { \ - UCSR0B = BV(BIT_RXCIE0) | BV(BIT_UDRIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0); \ - } while (0) + #define SER_UART0_BUS_TXBEGIN #endif #ifndef SER_UART0_BUS_TXCHAR @@ -139,144 +102,101 @@ * Invoked to send one character. */ #define SER_UART0_BUS_TXCHAR(c) do { \ - UDR0 = (c); \ + US0_THR = (c); \ } while (0) #endif #ifndef SER_UART0_BUS_TXEND /** * Invoked as soon as the txfifo becomes empty - * - * - Keep both the receiver and the transmitter enabled - * - Keep the RX complete interrupt enabled - * - Disable the UDR empty interrupt */ - #define SER_UART0_BUS_TXEND do { \ - UCSR0B = BV(BIT_RXCIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0); \ - } while (0) + #define SER_UART0_BUS_TXEND #endif -#ifndef SER_UART0_BUS_TXOFF +/* End USART0 macros */ + +#ifndef SER_UART1_BUS_TXINIT /** - * \def SER_UART0_BUS_TXOFF - * - * Invoked after the last character has been transmitted + * Default TXINIT macro - invoked in uart1_init() * - * The default is no action. + * - Disable GPIO on USART1 tx/rx pins */ - #ifdef __doxygen__ - #define SER_UART0_BUS_TXOFF + #if !CPU_ARM_AT91SAM7S256 && !CPU_ARM_AT91SAM7X256 && !CPU_ARM_AT91SAM7X128 + #warning Check USART1 pins! #endif -#endif - -#ifndef SER_UART1_BUS_TXINIT - /** \sa SER_UART0_BUS_TXINIT */ #define SER_UART1_BUS_TXINIT do { \ - UCSR1B = BV(BIT_RXCIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1); \ + PIOA_PDR = BV(RXD1) | BV(TXD1); \ } while (0) + #endif + #ifndef SER_UART1_BUS_TXBEGIN - /** \sa SER_UART0_BUS_TXBEGIN */ - #define SER_UART1_BUS_TXBEGIN do { \ - UCSR1B = BV(BIT_RXCIE1) | BV(BIT_UDRIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1); \ - } while (0) + /** + * Invoked before starting a transmission + */ + #define SER_UART1_BUS_TXBEGIN #endif + #ifndef SER_UART1_BUS_TXCHAR - /** \sa SER_UART0_BUS_TXCHAR */ + /** + * Invoked to send one character. + */ #define SER_UART1_BUS_TXCHAR(c) do { \ - UDR1 = (c); \ + US1_THR = (c); \ } while (0) #endif + #ifndef SER_UART1_BUS_TXEND - /** \sa SER_UART0_BUS_TXEND */ - #define SER_UART1_BUS_TXEND do { \ - UCSR1B = BV(BIT_RXCIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1); \ - } while (0) -#endif -#ifndef SER_UART1_BUS_TXOFF /** - * \def SER_UART1_BUS_TXOFF - * - * \see SER_UART0_BUS_TXOFF + * Invoked as soon as the txfifo becomes empty */ - #ifdef __doxygen__ - #define SER_UART1_BUS_TXOFF - #endif + #define SER_UART1_BUS_TXEND #endif -/*\}*/ - /** - * \name Overridable SPI hooks - * - * These can be redefined in hw.h to implement - * special bus policies such as slave select pin handling, etc. - * - * \{ - */ -#ifndef SER_SPI_BUS_TXINIT +* \name Overridable SPI hooks +* +* These can be redefined in hw.h to implement +* special bus policies such as slave select pin handling, etc. +* +* \{ +*/ + +#ifndef SER_SPI0_BUS_TXINIT /** - * Default TXINIT macro - invoked in spi_init() - * The default is no action. - */ - #define SER_SPI_BUS_TXINIT + * Default TXINIT macro - invoked in spi_init() + * The default is no action. + */ + #define SER_SPI0_BUS_TXINIT #endif -#ifndef SER_SPI_BUS_TXCLOSE +#ifndef SER_SPI0_BUS_TXCLOSE /** - * Invoked after the last character has been transmitted. - * The default is no action. - */ - #define SER_SPI_BUS_TXCLOSE + * Invoked after the last character has been transmitted. + * The default is no action. + */ + #define SER_SPI0_BUS_TXCLOSE #endif -/*\}*/ +#if CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7X256 -/* SPI port and pin configuration */ -#if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103 || CPU_AVR_ATMEGA1281 - #define SPI_PORT PORTB - #define SPI_DDR DDRB - #define SPI_SS_BIT PB0 - #define SPI_SCK_BIT PB1 - #define SPI_MOSI_BIT PB2 - #define SPI_MISO_BIT PB3 -#elif CPU_AVR_ATMEGA8 - #define SPI_PORT PORTB - #define SPI_DDR DDRB - #define SPI_SS_BIT PB2 - #define SPI_SCK_BIT PB5 - #define SPI_MOSI_BIT PB3 - #define SPI_MISO_BIT PB4 -#else - #error Unknown architecture -#endif + #ifndef SER_SPI1_BUS_TXINIT + /** + * Default TXINIT macro - invoked in spi_init() + * The default is no action. + */ + #define SER_SPI1_BUS_TXINIT + #endif -/* USART register definitions */ -#if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA1281 - #define AVR_HAS_UART1 1 -#elif CPU_AVR_ATMEGA8 - #define AVR_HAS_UART1 0 - #define UCSR0A UCSRA - #define UCSR0B UCSRB - #define UCSR0C UCSRC - #define UDR0 UDR - #define UBRR0L UBRRL - #define UBRR0H UBRRH - #define SIG_UART0_DATA SIG_UART_DATA - #define SIG_UART0_RECV SIG_UART_RECV - #define SIG_UART0_TRANS SIG_UART_TRANS -#elif CPU_AVR_ATMEGA103 - #define AVR_HAS_UART1 0 - #define UCSR0B UCR - #define UDR0 UDR - #define UCSR0A USR - #define UBRR0L UBRR - #define SIG_UART0_DATA SIG_UART_DATA - #define SIG_UART0_RECV SIG_UART_RECV - #define SIG_UART0_TRANS SIG_UART_TRANS -#else - #error Unknown architecture + #ifndef SER_SPI1_BUS_TXCLOSE + /** + * Invoked after the last character has been transmitted. + * The default is no action. + */ + #define SER_SPI1_BUS_TXCLOSE + #endif #endif +/*\}*/ /** @@ -302,13 +222,16 @@ extern struct Serial ser_handles[SER_CNT]; /* TX and RX buffers */ static unsigned char uart0_txbuffer[CONFIG_UART0_TXBUFSIZE]; static unsigned char uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE]; -#if AVR_HAS_UART1 - static unsigned char uart1_txbuffer[CONFIG_UART1_TXBUFSIZE]; - static unsigned char uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE]; -#endif -static unsigned char spi_txbuffer[CONFIG_SPI_TXBUFSIZE]; -static unsigned char spi_rxbuffer[CONFIG_SPI_RXBUFSIZE]; +static unsigned char uart1_txbuffer[CONFIG_UART1_TXBUFSIZE]; +static unsigned char uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE]; + +static unsigned char spi0_txbuffer[CONFIG_SPI0_TXBUFSIZE]; +static unsigned char spi0_rxbuffer[CONFIG_SPI0_RXBUFSIZE]; +#if CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7X256 +static unsigned char spi1_txbuffer[CONFIG_SPI1_TXBUFSIZE]; +static unsigned char spi1_rxbuffer[CONFIG_SPI1_RXBUFSIZE]; +#endif /** * Internal hardware state structure @@ -326,7 +249,7 @@ static unsigned char spi_rxbuffer[CONFIG_SPI_RXBUFSIZE]; * is done by spi_starttx()). We do this *only* if a transfer is * not already started. */ -struct AvrSerial +struct ArmSerial { struct SerialHardware hw; volatile bool sending; @@ -341,33 +264,60 @@ struct AvrSerial * (and hopefully faster) code. */ struct Serial *ser_uart0 = &ser_handles[SER_UART0]; -#if AVR_HAS_UART1 struct Serial *ser_uart1 = &ser_handles[SER_UART1]; -#endif -struct Serial *ser_spi = &ser_handles[SER_SPI]; - +struct Serial *ser_spi0 = &ser_handles[SER_SPI0]; +#if CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7X256 +struct Serial *ser_spi1 = &ser_handles[SER_SPI1]; +#endif +static void uart0_irq_dispatcher(void); +static void uart1_irq_dispatcher(void); +static void spi0_irq_handler(void); +#if CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7X256 +static void spi1_irq_handler(void); +#endif /* - * Callbacks + * Callbacks for USART0 */ static void uart0_init( UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct Serial *, ser)) { + US0_IDR = 0xFFFFFFFF; + /* Set the vector. */ + AIC_SVR(US0_ID) = uart0_irq_dispatcher; + /* Initialize to edge triggered with defined priority. */ + AIC_SMR(US0_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED | SERIRQ_PRIORITY; + PMC_PCER = BV(US0_ID); + + /* + * - Reset USART0 + * - Set serial param: mode Normal, 8bit data, 1bit stop, parity none + * - Enable both the receiver and the transmitter + * - Enable only the RX complete interrupt + */ + US0_CR = BV(US_RSTRX) | BV(US_RSTTX); + US0_MR = US_CHMODE_NORMAL | US_CHRL_8 | US_NBSTOP_1 | US_PAR_NO; + US0_CR = BV(US_RXEN) | BV(US_TXEN); + US0_IER = BV(US_RXRDY); + SER_UART0_BUS_TXINIT; - RTS_ON; + + /* Enable the USART IRQ */ + AIC_IECR = BV(US0_ID); + SER_STROBE_INIT; } static void uart0_cleanup(UNUSED_ARG(struct SerialHardware *, _hw)) { - UCSR0B = 0; + US0_CR = BV(US_RSTRX) | BV(US_RSTTX) | BV(US_RXDIS) | BV(US_TXDIS) | BV(US_RSTSTA); } static void uart0_enabletxirq(struct SerialHardware *_hw) { - struct AvrSerial *hw = (struct AvrSerial *)_hw; + struct ArmSerial *hw = (struct ArmSerial *)_hw; /* * WARNING: racy code here! The tx interrupt sets hw->sending to false @@ -377,202 +327,327 @@ static void uart0_enabletxirq(struct SerialHardware *_hw) if (!hw->sending) { hw->sending = true; + /* + * - Enable the transmitter + * - Enable TX empty interrupt + */ SER_UART0_BUS_TXBEGIN; + US0_IER = BV(US_TXEMPTY); } } static void uart0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate) { /* Compute baud-rate period */ - uint16_t period = (((CLOCK_FREQ / 16UL) + (rate / 2)) / rate) - 1; - -#if !CPU_AVR_ATMEGA103 - UBRR0H = (period) >> 8; -#endif - UBRR0L = (period); - + US0_BRGR = CLOCK_FREQ / (16 * rate); //DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);) } static void uart0_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity) { -#if !CPU_AVR_ATMEGA103 - UCSR0C = (UCSR0C & ~(BV(UPM01) | BV(UPM00))) | ((parity) << UPM00); -#endif -} - -#if AVR_HAS_UART1 + US0_MR &= ~US_PAR_MASK; + /* Set UART parity */ + switch(parity) + { + case SER_PARITY_NONE: + { + /* Parity none. */ + US0_MR |= US_PAR_NO; + break; + } + case SER_PARITY_EVEN: + { + /* Even parity. */ + US0_MR |= US_PAR_EVEN; + break; + } + case SER_PARITY_ODD: + { + /* Odd parity. */ + US0_MR |= US_PAR_ODD; + break; + } + default: + ASSERT(0); + } +} +/* + * Callbacks for USART1 + */ static void uart1_init( UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct Serial *, ser)) { + US1_IDR = 0xFFFFFFFF; + /* Set the vector. */ + AIC_SVR(US1_ID) = uart1_irq_dispatcher; + /* Initialize to edge triggered with defined priority. */ + AIC_SMR(US1_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED | SERIRQ_PRIORITY; + PMC_PCER = BV(US1_ID); + + /* + * - Reset USART1 + * - Set serial param: mode Normal, 8bit data, 1bit stop, parity none + * - Enable both the receiver and the transmitter + * - Enable only the RX complete interrupt + */ + US1_CR = BV(US_RSTRX) | BV(US_RSTTX); + US1_MR = US_CHMODE_NORMAL | US_CHRL_8 | US_NBSTOP_1 | US_PAR_NO; + US1_CR = BV(US_RXEN) | BV(US_TXEN); + US1_IER = BV(US_RXRDY); + SER_UART1_BUS_TXINIT; - RTS_ON; + + /* Enable the USART IRQ */ + AIC_IECR = BV(US1_ID); + SER_STROBE_INIT; } static void uart1_cleanup(UNUSED_ARG(struct SerialHardware *, _hw)) { - UCSR1B = 0; + US1_CR = BV(US_RSTRX) | BV(US_RSTTX) | BV(US_RXDIS) | BV(US_TXDIS) | BV(US_RSTSTA); } static void uart1_enabletxirq(struct SerialHardware *_hw) { - struct AvrSerial *hw = (struct AvrSerial *)_hw; + struct ArmSerial *hw = (struct ArmSerial *)_hw; /* - * WARNING: racy code here! The tx interrupt - * sets hw->sending to false when it runs with - * an empty fifo. The order of the statements - * in the if-block matters. + * WARNING: racy code here! The tx interrupt sets hw->sending to false + * when it runs with an empty fifo. The order of statements in the + * if-block matters. */ if (!hw->sending) { hw->sending = true; + /* + * - Enable the transmitter + * - Enable TX empty interrupt + */ SER_UART1_BUS_TXBEGIN; + US1_IER = BV(US_TXEMPTY); } } static void uart1_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate) { /* Compute baud-rate period */ - uint16_t period = (((CLOCK_FREQ / 16UL) + (rate / 2)) / rate) - 1; - - UBRR1H = (period) >> 8; - UBRR1L = (period); - - //DB(kprintf("uart1_setbaudrate(rate=%ld): period=%d\n", rate, period);) + US1_BRGR = CLOCK_FREQ / (16 * rate); + //DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);) } static void uart1_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity) { - UCSR1C = (UCSR1C & ~(BV(UPM11) | BV(UPM10))) | ((parity) << UPM10); -} + US1_MR &= ~US_PAR_MASK; + /* Set UART parity */ + switch(parity) + { + case SER_PARITY_NONE: + { + /* Parity none. */ + US1_MR |= US_PAR_NO; + break; + } + case SER_PARITY_EVEN: + { + /* Even parity. */ + US1_MR |= US_PAR_EVEN; + break; + } + case SER_PARITY_ODD: + { + /* Odd parity. */ + US1_MR |= US_PAR_ODD; + break; + } + default: + ASSERT(0); + } -#endif // AVR_HAS_UART1 +} -static void spi_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct Serial *, ser)) +/* SPI driver */ +static void spi0_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct Serial *, ser)) { + /* Disable PIO on SPI pins */ + PIOA_PDR = BV(SPI0_SPCK) | BV(SPI0_MOSI) | BV(SPI0_MISO); + + /* Reset device */ + SPI0_CR = BV(SPI_SWRST); + /* - * Set MOSI and SCK ports out, MISO in. - * - * The ATmega64/128 datasheet explicitly states that the input/output - * state of the SPI pins is not significant, as when the SPI is - * active the I/O port are overrided. - * This is *blatantly FALSE*. - * - * Moreover, the MISO pin on the board_kc *must* be in high impedance - * state even when the SPI is off, because the line is wired together - * with the KBus serial RX, and the transmitter of the slave boards - * would be unable to drive the line. + * Set SPI to master mode, fixed peripheral select, chip select directly connected to a peripheral device, + * SPI clock set to MCK, mode fault detection disabled, loopback disable, NPCS0 active, Delay between CS = 0 */ - ATOMIC(SPI_DDR |= (BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT))); + SPI0_MR = BV(SPI_MSTR) | BV(SPI_MODFDIS); /* - * If the SPI master mode is activated and the SS pin is in input and tied low, - * the SPI hardware will automatically switch to slave mode! - * For proper communication this pins should therefore be: - * - as output - * - as input but tied high forever! - * This driver set the pin as output. + * Set SPI mode. + * At reset clock division factor is set to 0, that is + * *forbidden*. Set SPI clock to minimum to keep it valid. */ - #warning SPI SS pin set as output for proper operation, check schematics for possible conflicts. - ATOMIC(SPI_DDR |= BV(SPI_SS_BIT)); + SPI0_CSR0 = BV(SPI_NCPHA) | (255 << SPI_SCBR_SHIFT); - ATOMIC(SPI_DDR &= ~BV(SPI_MISO_BIT)); - /* Enable SPI, IRQ on, Master */ - SPCR = BV(SPE) | BV(SPIE) | BV(MSTR); + /* Disable all irqs */ + SPI0_IDR = 0xFFFFFFFF; + /* Set the vector. */ + AIC_SVR(SPI0_ID) = spi0_irq_handler; + /* Initialize to edge triggered with defined priority. */ + AIC_SMR(SPI0_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED | SERIRQ_PRIORITY; + /* Enable the USART IRQ */ + AIC_IECR = BV(SPI0_ID); + PMC_PCER = BV(SPI0_ID); - /* Set data order */ - #if CONFIG_SPI_DATA_ORDER == SER_LSB_FIRST - SPCR |= BV(DORD); - #endif + /* Enable interrupt on tx buffer empty */ + SPI0_IER = BV(SPI_TXEMPTY); - /* Set SPI clock rate */ - #if CONFIG_SPI_CLOCK_DIV == 128 - SPCR |= (BV(SPR1) | BV(SPR0)); - #elif (CONFIG_SPI_CLOCK_DIV == 64 || CONFIG_SPI_CLOCK_DIV == 32) - SPCR |= BV(SPR1); - #elif (CONFIG_SPI_CLOCK_DIV == 16 || CONFIG_SPI_CLOCK_DIV == 8) - SPCR |= BV(SPR0); - #elif (CONFIG_SPI_CLOCK_DIV == 4 || CONFIG_SPI_CLOCK_DIV == 2) - // SPR0 & SDPR1 both at 0 - #else - #error Unsupported SPI clock division factor. - #endif + /* Enable SPI */ + SPI0_CR = BV(SPI_SPIEN); - /* Set SPI2X bit (spi double frequency) */ - #if (CONFIG_SPI_CLOCK_DIV == 128 || CONFIG_SPI_CLOCK_DIV == 64 \ - || CONFIG_SPI_CLOCK_DIV == 16 || CONFIG_SPI_CLOCK_DIV == 4) - SPSR &= ~BV(SPI2X); - #elif (CONFIG_SPI_CLOCK_DIV == 32 || CONFIG_SPI_CLOCK_DIV == 8 || CONFIG_SPI_CLOCK_DIV == 2) - SPSR |= BV(SPI2X); - #else - #error Unsupported SPI clock division factor. - #endif - /* Set clock polarity */ - #if CONFIG_SPI_CLOCK_POL == 1 - SPCR |= BV(CPOL); - #endif + SER_SPI0_BUS_TXINIT; - /* Set clock phase */ - #if CONFIG_SPI_CLOCK_PHASE == 1 - SPCR |= BV(CPHA); - #endif - SER_SPI_BUS_TXINIT; + SER_STROBE_INIT; +} + +static void spi0_cleanup(UNUSED_ARG(struct SerialHardware *, _hw)) +{ + /* Disable SPI */ + SPI0_CR = BV(SPI_SPIDIS); + + /* Disable all irqs */ + SPI0_IDR = 0xFFFFFFFF; + + SER_SPI0_BUS_TXCLOSE; + + /* Enable PIO on SPI pins */ + PIOA_PER = BV(SPI0_SPCK) | BV(SPI0_MOSI) | BV(SPI0_MISO); +} + +static void spi0_starttx(struct SerialHardware *_hw) +{ + struct ArmSerial *hw = (struct ArmSerial *)_hw; + + cpuflags_t flags; + IRQ_SAVE_DISABLE(flags); + + /* Send data only if the SPI is not already transmitting */ + if (!hw->sending && !fifo_isempty(&ser_spi0->txfifo)) + { + hw->sending = true; + SPI0_TDR = fifo_pop(&ser_spi0->txfifo); + } + + IRQ_RESTORE(flags); +} + +static void spi0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate) +{ + SPI0_CSR0 &= ~SPI_SCBR; + + ASSERT((uint8_t)DIV_ROUND(CLOCK_FREQ, rate)); + SPI0_CSR0 |= DIV_ROUND(CLOCK_FREQ, rate) << SPI_SCBR_SHIFT; +} + +#if CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7X256 +/* SPI driver */ +static void spi1_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct Serial *, ser)) +{ + /* Disable PIO on SPI pins */ + PIOA_PDR = BV(SPI1_SPCK) | BV(SPI1_MOSI) | BV(SPI1_MISO); + + /* Reset device */ + SPI1_CR = BV(SPI_SWRST); + +/* + * Set SPI to master mode, fixed peripheral select, chip select directly connected to a peripheral device, + * SPI clock set to MCK, mode fault detection disabled, loopback disable, NPCS0 active, Delay between CS = 0 + */ + SPI1_MR = BV(SPI_MSTR) | BV(SPI_MODFDIS); + + /* + * Set SPI mode. + * At reset clock division factor is set to 0, that is + * *forbidden*. Set SPI clock to minimum to keep it valid. + */ + SPI1_CSR0 = BV(SPI_NCPHA) | (255 << SPI_SCBR_SHIFT); + + /* Disable all irqs */ + SPI1_IDR = 0xFFFFFFFF; + /* Set the vector. */ + AIC_SVR(SPI1_ID) = spi1_irq_handler; + /* Initialize to edge triggered with defined priority. */ + AIC_SMR(SPI1_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED | SERIRQ_PRIORITY; + /* Enable the USART IRQ */ + AIC_IECR = BV(SPI1_ID); + PMC_PCER = BV(SPI1_ID); + + /* Enable interrupt on tx buffer empty */ + SPI1_IER = BV(SPI_TXEMPTY); + + /* Enable SPI */ + SPI1_CR = BV(SPI_SPIEN); + + + SER_SPI1_BUS_TXINIT; SER_STROBE_INIT; } -static void spi_cleanup(UNUSED_ARG(struct SerialHardware *, _hw)) +static void spi1_cleanup(UNUSED_ARG(struct SerialHardware *, _hw)) { - SPCR = 0; + /* Disable SPI */ + SPI1_CR = BV(SPI_SPIDIS); + + /* Disable all irqs */ + SPI1_IDR = 0xFFFFFFFF; - SER_SPI_BUS_TXCLOSE; + SER_SPI1_BUS_TXCLOSE; - /* Set all pins as inputs */ - ATOMIC(SPI_DDR &= ~(BV(SPI_MISO_BIT) | BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT) | BV(SPI_SS_BIT))); + /* Enable PIO on SPI pins */ + PIOA_PER = BV(SPI1_SPCK) | BV(SPI1_MOSI) | BV(SPI1_MISO); } -static void spi_starttx(struct SerialHardware *_hw) +static void spi1_starttx(struct SerialHardware *_hw) { - struct AvrSerial *hw = (struct AvrSerial *)_hw; + struct ArmSerial *hw = (struct ArmSerial *)_hw; cpuflags_t flags; IRQ_SAVE_DISABLE(flags); /* Send data only if the SPI is not already transmitting */ - if (!hw->sending && !fifo_isempty(&ser_spi->txfifo)) + if (!hw->sending && !fifo_isempty(&ser_spi1->txfifo)) { hw->sending = true; - SPDR = fifo_pop(&ser_spi->txfifo); + SPI1_TDR = fifo_pop(&ser_spi1->txfifo); } IRQ_RESTORE(flags); } -static void spi_setbaudrate( - UNUSED_ARG(struct SerialHardware *, _hw), - UNUSED_ARG(unsigned long, rate)) +static void spi1_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate) { - // nop + SPI1_CSR0 &= ~SPI_SCBR; + + ASSERT((uint8_t)DIV_ROUND(CLOCK_FREQ, rate)); + SPI1_CSR0 |= DIV_ROUND(CLOCK_FREQ, rate) << SPI_SCBR_SHIFT; } +#endif static void spi_setparity(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(int, parity)) { // nop } + static bool tx_sending(struct SerialHardware* _hw) { - struct AvrSerial *hw = (struct AvrSerial *)_hw; + struct ArmSerial *hw = (struct ArmSerial *)_hw; return hw->sending; } - - // FIXME: move into compiler.h? Ditch? #if COMPILER_C99 #define C99INIT(name,val) .name = val @@ -596,7 +671,6 @@ static const struct SerialHardwareVT UART0_VT = C99INIT(txSending, tx_sending), }; -#if AVR_HAS_UART1 static const struct SerialHardwareVT UART1_VT = { C99INIT(init, uart1_init), @@ -606,19 +680,29 @@ static const struct SerialHardwareVT UART1_VT = C99INIT(txStart, uart1_enabletxirq), C99INIT(txSending, tx_sending), }; -#endif // AVR_HAS_UART1 -static const struct SerialHardwareVT SPI_VT = +static const struct SerialHardwareVT SPI0_VT = +{ + C99INIT(init, spi0_init), + C99INIT(cleanup, spi0_cleanup), + C99INIT(setBaudrate, spi0_setbaudrate), + C99INIT(setParity, spi_setparity), + C99INIT(txStart, spi0_starttx), + C99INIT(txSending, tx_sending), +}; +#if CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7X128 +static const struct SerialHardwareVT SPI1_VT = { - C99INIT(init, spi_init), - C99INIT(cleanup, spi_cleanup), - C99INIT(setBaudrate, spi_setbaudrate), + C99INIT(init, spi1_init), + C99INIT(cleanup, spi1_cleanup), + C99INIT(setBaudrate, spi1_setbaudrate), C99INIT(setParity, spi_setparity), - C99INIT(txStart, spi_starttx), + C99INIT(txStart, spi1_starttx), C99INIT(txSending, tx_sending), }; +#endif -static struct AvrSerial UARTDescs[SER_CNT] = +static struct ArmSerial UARTDescs[SER_CNT] = { { C99INIT(hw, /**/) { @@ -630,7 +714,6 @@ static struct AvrSerial UARTDescs[SER_CNT] = }, C99INIT(sending, false), }, -#if AVR_HAS_UART1 { C99INIT(hw, /**/) { C99INIT(table, &UART1_VT), @@ -641,17 +724,30 @@ static struct AvrSerial UARTDescs[SER_CNT] = }, C99INIT(sending, false), }, -#endif + { C99INIT(hw, /**/) { - C99INIT(table, &SPI_VT), - C99INIT(txbuffer, spi_txbuffer), - C99INIT(rxbuffer, spi_rxbuffer), - C99INIT(txbuffer_size, sizeof(spi_txbuffer)), - C99INIT(rxbuffer_size, sizeof(spi_rxbuffer)), + C99INIT(table, &SPI0_VT), + C99INIT(txbuffer, spi0_txbuffer), + C99INIT(rxbuffer, spi0_rxbuffer), + C99INIT(txbuffer_size, sizeof(spi0_txbuffer)), + C99INIT(rxbuffer_size, sizeof(spi0_rxbuffer)), + }, + C99INIT(sending, false), + }, + #if CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7X128 + { + C99INIT(hw, /**/) { + C99INIT(table, &SPI1_VT), + C99INIT(txbuffer, spi1_txbuffer), + C99INIT(rxbuffer, spi1_rxbuffer), + C99INIT(txbuffer_size, sizeof(spi1_txbuffer)), + C99INIT(rxbuffer_size, sizeof(spi1_rxbuffer)), }, C99INIT(sending, false), } + + #endif }; struct SerialHardware *ser_hw_getdesc(int unit) @@ -660,28 +756,10 @@ struct SerialHardware *ser_hw_getdesc(int unit) return &UARTDescs[unit].hw; } - -/* - * Interrupt handlers - */ - -#if CONFIG_SER_HWHANDSHAKE - -/// This interrupt is triggered when the CTS line goes high -SIGNAL(SIG_CTS) -{ - // Re-enable UDR empty interrupt and TX, then disable CTS interrupt - UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); - EIMSK &= ~EIMSKF_CTS; -} - -#endif // CONFIG_SER_HWHANDSHAKE - - /** * Serial 0 TX interrupt handler */ -SIGNAL(USART0_UDRE_vect) +static void uart0_irq_tx(void) { SER_STROBE_ON; @@ -689,21 +767,13 @@ SIGNAL(USART0_UDRE_vect) if (fifo_isempty(txfifo)) { + /* + * - Disable the TX empty interrupts + */ + US0_IDR = BV(US_TXEMPTY); SER_UART0_BUS_TXEND; -#ifndef SER_UART0_BUS_TXOFF UARTDescs[SER_UART0].sending = false; -#endif - } -#if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103 - else if (!IS_CTS_ON) - { - // Disable rx interrupt and tx, enable CTS interrupt - // UNTESTED - UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN); - EIFR |= EIMSKF_CTS; - EIMSK |= EIMSKF_CTS; } -#endif else { char c = fifo_pop(txfifo); @@ -713,46 +783,47 @@ SIGNAL(USART0_UDRE_vect) SER_STROBE_OFF; } -#ifdef SER_UART0_BUS_TXOFF /** - * Serial port 0 TX complete interrupt handler. - * - * This IRQ is usually disabled. The UDR-empty interrupt - * enables it when there's no more data to transmit. - * We need to wait until the last character has been - * transmitted before switching the 485 transceiver to - * receive mode. - * - * The txfifo might have been refilled by putchar() while - * we were waiting for the transmission complete interrupt. - * In this case, we must restart the UDR empty interrupt, - * otherwise we'd stop the serial port with some data - * still pending in the buffer. + * Serial 0 RX complete interrupt handler. */ -SIGNAL(SIG_UART0_TRANS) +static void uart0_irq_rx(void) { SER_STROBE_ON; - struct FIFOBuffer * const txfifo = &ser_uart0->txfifo; - if (fifo_isempty(txfifo)) - { - SER_UART0_BUS_TXOFF; - UARTDescs[SER_UART0].sending = false; - } + /* Should be read before US_CRS */ + ser_uart0->status |= US0_CSR & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR); + + char c = US0_RHR; + struct FIFOBuffer * const rxfifo = &ser_uart0->rxfifo; + + if (fifo_isfull(rxfifo)) + ser_uart0->status |= SERRF_RXFIFOOVERRUN; else - UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); + fifo_push(rxfifo, c); SER_STROBE_OFF; } -#endif /* SER_UART0_BUS_TXOFF */ +/** + * Serial IRQ dispatcher for USART0. + */ +static void uart0_irq_dispatcher(void) __attribute__ ((interrupt)); +static void uart0_irq_dispatcher(void) +{ + if (US0_CSR & BV(US_RXRDY)) + uart0_irq_rx(); -#if AVR_HAS_UART1 + if (US0_CSR & BV(US_TXEMPTY)) + uart0_irq_tx(); + + /* Inform hw that we have served the IRQ */ + AIC_EOICR = 0; +} /** * Serial 1 TX interrupt handler */ -SIGNAL(USART1_UDRE_vect) +static void uart1_irq_tx(void) { SER_STROBE_ON; @@ -760,21 +831,13 @@ SIGNAL(USART1_UDRE_vect) if (fifo_isempty(txfifo)) { + /* + * - Disable the TX empty interrupts + */ + US1_IDR = BV(US_TXEMPTY); SER_UART1_BUS_TXEND; -#ifndef SER_UART1_BUS_TXOFF UARTDescs[SER_UART1].sending = false; -#endif } -#if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103 - else if (!IS_CTS_ON) - { - // Disable rx interrupt and tx, enable CTS interrupt - // UNTESTED - UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); - EIFR |= EIMSKF_CTS; - EIMSK |= EIMSKF_CTS; - } -#endif else { char c = fifo_pop(txfifo); @@ -784,156 +847,100 @@ SIGNAL(USART1_UDRE_vect) SER_STROBE_OFF; } -#ifdef SER_UART1_BUS_TXOFF /** - * Serial port 1 TX complete interrupt handler. - * - * \sa port 0 TX complete handler. + * Serial 1 RX complete interrupt handler. */ -SIGNAL(SIG_UART1_TRANS) +static void uart1_irq_rx(void) { SER_STROBE_ON; - struct FIFOBuffer * const txfifo = &ser_uart1->txfifo; - if (fifo_isempty(txfifo)) - { - SER_UART1_BUS_TXOFF; - UARTDescs[SER_UART1].sending = false; - } + /* Should be read before US_CRS */ + ser_uart1->status |= US1_CSR & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR); + + char c = US1_RHR; + struct FIFOBuffer * const rxfifo = &ser_uart1->rxfifo; + + if (fifo_isfull(rxfifo)) + ser_uart1->status |= SERRF_RXFIFOOVERRUN; else - UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); + fifo_push(rxfifo, c); SER_STROBE_OFF; } -#endif /* SER_UART1_BUS_TXOFF */ - -#endif // AVR_HAS_UART1 - /** - * Serial 0 RX complete interrupt handler. - * - * This handler is interruptible. - * Interrupt are reenabled as soon as recv complete interrupt is - * disabled. Using INTERRUPT() is troublesome when the serial - * is heavily loaded, because an interrupt could be retriggered - * when executing the handler prologue before RXCIE is disabled. - * - * \note The code that re-enables interrupts is commented out - * because in some nasty cases the interrupt is retriggered. - * This is probably due to the RXC flag being set before - * RXCIE is cleared. Unfortunately the RXC flag is read-only - * and can't be cleared by code. + * Serial IRQ dispatcher for USART1. */ -SIGNAL(USART0_RX_vect) +static void uart1_irq_dispatcher(void) __attribute__ ((interrupt)); +static void uart1_irq_dispatcher(void) { - SER_STROBE_ON; - - /* Disable Recv complete IRQ */ - //UCSR0B &= ~BV(RXCIE); - //IRQ_ENABLE; - - /* Should be read before UDR */ - ser_uart0->status |= UCSR0A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR); - - /* To clear the RXC flag we must _always_ read the UDR even when we're - * not going to accept the incoming data, otherwise a new interrupt - * will occur once the handler terminates. - */ - char c = UDR0; - struct FIFOBuffer * const rxfifo = &ser_uart0->rxfifo; + if (US1_CSR & BV(US_RXRDY)) + uart1_irq_rx(); - if (fifo_isfull(rxfifo)) - ser_uart0->status |= SERRF_RXFIFOOVERRUN; - else - { - fifo_push(rxfifo, c); -#if CONFIG_SER_HWHANDSHAKE - if (fifo_isfull(rxfifo)) - RTS_OFF; -#endif - } + if (US1_CSR & BV(US_TXEMPTY)) + uart1_irq_tx(); - /* Reenable receive complete int */ - //IRQ_DISABLE; - //UCSR0B |= BV(RXCIE); - - SER_STROBE_OFF; + /* Inform hw that we have served the IRQ */ + AIC_EOICR = 0; } - -#if AVR_HAS_UART1 - /** - * Serial 1 RX complete interrupt handler. - * - * This handler is interruptible. - * Interrupt are reenabled as soon as recv complete interrupt is - * disabled. Using INTERRUPT() is troublesome when the serial - * is heavily loaded, because an interrupt could be retriggered - * when executing the handler prologue before RXCIE is disabled. - * - * \see SIGNAL(USART1_RX_vect) + * SPI0 interrupt handler */ -SIGNAL(USART1_RX_vect) +static void spi0_irq_handler(void) __attribute__ ((interrupt)); +static void spi0_irq_handler(void) { SER_STROBE_ON; - /* Disable Recv complete IRQ */ - //UCSR1B &= ~BV(RXCIE); - //IRQ_ENABLE; - - /* Should be read before UDR */ - ser_uart1->status |= UCSR1A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR); - - /* To avoid an IRQ storm, we must _always_ read the UDR even when we're - * not going to accept the incoming data - */ - char c = UDR1; - struct FIFOBuffer * const rxfifo = &ser_uart1->rxfifo; - //ASSERT_VALID_FIFO(rxfifo); + char c = SPI0_RDR; + /* Read incoming byte. */ + if (!fifo_isfull(&ser_spi0->rxfifo)) + fifo_push(&ser_spi0->rxfifo, c); + /* + * FIXME + else + ser_spi0->status |= SERRF_RXFIFOOVERRUN; + */ - if (UNLIKELY(fifo_isfull(rxfifo))) - ser_uart1->status |= SERRF_RXFIFOOVERRUN; + /* Send */ + if (!fifo_isempty(&ser_spi0->txfifo)) + SPI0_TDR = fifo_pop(&ser_spi0->txfifo); else - { - fifo_push(rxfifo, c); -#if CONFIG_SER_HWHANDSHAKE - if (fifo_isfull(rxfifo)) - RTS_OFF; -#endif - } - /* Re-enable receive complete int */ - //IRQ_DISABLE; - //UCSR1B |= BV(RXCIE); + UARTDescs[SER_SPI0].sending = false; + /* Inform hw that we have served the IRQ */ + AIC_EOICR = 0; SER_STROBE_OFF; } -#endif // AVR_HAS_UART1 - +#if CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7X128 /** - * SPI interrupt handler + * SPI1 interrupt handler */ -SIGNAL(SIG_SPI) +static void spi1_irq_handler(void) __attribute__ ((interrupt)); +static void spi1_irq_handler(void) { SER_STROBE_ON; + char c = SPI1_RDR; /* Read incoming byte. */ - if (!fifo_isfull(&ser_spi->rxfifo)) - fifo_push(&ser_spi->rxfifo, SPDR); + if (!fifo_isfull(&ser_spi1->rxfifo)) + fifo_push(&ser_spi1->rxfifo, c); /* * FIXME else - ser_spi->status |= SERRF_RXFIFOOVERRUN; + ser_spi1->status |= SERRF_RXFIFOOVERRUN; */ /* Send */ - if (!fifo_isempty(&ser_spi->txfifo)) - SPDR = fifo_pop(&ser_spi->txfifo); + if (!fifo_isempty(&ser_spi1->txfifo)) + SPI1_TDR = fifo_pop(&ser_spi1->txfifo); else - UARTDescs[SER_SPI].sending = false; + UARTDescs[SER_SPI1].sending = false; + /* Inform hw that we have served the IRQ */ + AIC_EOICR = 0; SER_STROBE_OFF; } +#endif