X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=cpu%2Farm%2Fdrv%2Fser_at91.c;h=82320bdf1ad1edc699258faa37af2cc678c1773f;hb=faed9d33b0a6bd6c2376e313fa3b73512c545caa;hp=c381b9e0e305360395d0f42ce88195ec9e16df57;hpb=0c34de8478ce67d95f6bef3d239b76204c1dbdc2;p=bertos.git diff --git a/cpu/arm/drv/ser_at91.c b/cpu/arm/drv/ser_at91.c index c381b9e0..82320bdf 100644 --- a/cpu/arm/drv/ser_at91.c +++ b/cpu/arm/drv/ser_at91.c @@ -34,7 +34,7 @@ * \brief ARM UART and SPI I/O driver * * - * \version $Id: ser_amr.c 18280 2007-10-11 15:14:20Z asterix $ + * \version $Id: ser_at91.c 20881 2008-03-04 14:07:02Z batt $ * \author Daniele Basile */ @@ -75,45 +75,17 @@ * \{ */ -#ifndef SER_UART0_IRQ_INIT - /** - * Default IRQ INIT macro - invoked in uart0_init() - * - * - Disable all interrupt - * - Register USART0 interrupt - * - Enable USART0 clock. - */ - #define SER_UART0_IRQ_INIT do { \ - US0_IDR = 0xFFFFFFFF; \ - /* Set the vector. */ \ - AIC_SVR(US0_ID) = uart0_irq_dispatcher; \ - /* Initialize to edge triggered with defined priority. */ \ - AIC_SMR(US0_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED | SERIRQ_PRIORITY; \ - /* Enable the USART IRQ */ \ - AIC_IECR = BV(US0_ID); \ - PMC_PCER = BV(US0_ID); \ - } while (0) -#endif - #ifndef SER_UART0_BUS_TXINIT /** * Default TXINIT macro - invoked in uart0_init() * * - Disable GPIO on USART0 tx/rx pins - * - Reset USART0 - * - Set serial param: mode Normal, 8bit data, 1bit stop - * - Enable both the receiver and the transmitter - * - Enable only the RX complete interrupt */ - #if !CPU_ARM_AT91SAM7S256 + #if !CPU_ARM_AT91SAM7S256 && !CPU_ARM_AT91SAM7X256 && !CPU_ARM_AT91SAM7X128 #warning Check USART0 pins! #endif #define SER_UART0_BUS_TXINIT do { \ PIOA_PDR = BV(RXD0) | BV(TXD0); \ - US0_CR = BV(US_RSTRX) | BV(US_RSTTX); \ - US0_MR = US_CHMODE_NORMAL | US_CHRL_8 | US_NBSTOP_1; \ - US0_CR = BV(US_RXEN) | BV(US_TXEN); \ - US0_IER = BV(US_RXRDY); \ } while (0) #endif @@ -121,14 +93,8 @@ #ifndef SER_UART0_BUS_TXBEGIN /** * Invoked before starting a transmission - * - * - Enable both the receiver and the transmitter - * - Enable both the RX complete and TX empty interrupts */ - #define SER_UART0_BUS_TXBEGIN do { \ - US0_CR = BV(US_RXEN) | BV(US_TXEN); \ - US0_IER = BV(US_TXRDY) | BV(US_RXRDY); \ - } while (0) + #define SER_UART0_BUS_TXBEGIN #endif #ifndef SER_UART0_BUS_TXCHAR @@ -143,72 +109,96 @@ #ifndef SER_UART0_BUS_TXEND /** * Invoked as soon as the txfifo becomes empty - * - * - Keep both the receiver and the transmitter enabled - * - Keep the RX complete interrupt enabled - * - Disable the TX empty interrupts */ - #define SER_UART0_BUS_TXEND do { \ - US0_CR = BV(US_RXEN) | BV(US_TXEN); \ - US0_IER = BV(US_RXRDY); \ - US0_IDR = BV(US_TXRDY); \ - } while (0) + #define SER_UART0_BUS_TXEND #endif /* End USART0 macros */ -#ifndef SER_UART1_IRQ_INIT - /** \sa SER_UART0_BUS_TXINIT */ - #define SER_UART1_IRQ_INIT do { \ - US1_IDR = 0xFFFFFFFF; \ - /* Set the vector. */ \ - AIC_SVR(US1_ID) = uart1_irq_dispatcher; \ - /* Initialize to edge triggered with defined priority. */ \ - AIC_SMR(US1_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED | SERIRQ_PRIORITY; \ - /* Enable the USART IRQ */ \ - AIC_IECR = BV(US1_ID); \ - PMC_PCER = BV(US1_ID); \ - } while (0) -#endif - #ifndef SER_UART1_BUS_TXINIT - /** \sa SER_UART1_BUS_TXINIT */ - #if !CPU_ARM_AT91SAM7S256 + /** + * Default TXINIT macro - invoked in uart1_init() + * + * - Disable GPIO on USART1 tx/rx pins + */ + #if !CPU_ARM_AT91SAM7S256 && !CPU_ARM_AT91SAM7X256 && !CPU_ARM_AT91SAM7X128 #warning Check USART1 pins! #endif #define SER_UART1_BUS_TXINIT do { \ PIOA_PDR = BV(RXD1) | BV(TXD1); \ - US1_CR = BV(US_RSTRX) | BV(US_RSTTX); \ - US1_MR = US_CHMODE_NORMAL | US_CHRL_8 | US_NBSTOP_1; \ - US1_CR = BV(US_RXEN) | BV(US_TXEN); \ - US1_IER = BV(US_RXRDY); \ } while (0) + #endif #ifndef SER_UART1_BUS_TXBEGIN - /** \sa SER_UART1_BUS_TXBEGIN */ - #define SER_UART1_BUS_TXBEGIN do { \ - US1_CR = BV(US_RXEN) | BV(US_TXEN); \ - US1_IER = BV(US_TXRDY) | BV(US_RXRDY); \ - } while (0) + /** + * Invoked before starting a transmission + */ + #define SER_UART1_BUS_TXBEGIN #endif #ifndef SER_UART1_BUS_TXCHAR - /** \sa SER_UART1_BUS_TXCHAR */ + /** + * Invoked to send one character. + */ #define SER_UART1_BUS_TXCHAR(c) do { \ US1_THR = (c); \ } while (0) #endif #ifndef SER_UART1_BUS_TXEND - /** \sa SER_UART1_BUS_TXEND */ - #define SER_UART1_BUS_TXEND do { \ - US1_CR = BV(US_RXEN) | BV(US_TXEN); \ - US1_IER = BV(US_RXRDY); \ - US1_IDR = BV(US_TXRDY); \ - } while (0) + /** + * Invoked as soon as the txfifo becomes empty + */ + #define SER_UART1_BUS_TXEND #endif +/** +* \name Overridable SPI hooks +* +* These can be redefined in hw.h to implement +* special bus policies such as slave select pin handling, etc. +* +* \{ +*/ + +#ifndef SER_SPI0_BUS_TXINIT + /** + * Default TXINIT macro - invoked in spi_init() + * The default is no action. + */ + #define SER_SPI0_BUS_TXINIT +#endif + +#ifndef SER_SPI0_BUS_TXCLOSE + /** + * Invoked after the last character has been transmitted. + * The default is no action. + */ + #define SER_SPI0_BUS_TXCLOSE +#endif + +#if CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7X256 + + #ifndef SER_SPI1_BUS_TXINIT + /** + * Default TXINIT macro - invoked in spi_init() + * The default is no action. + */ + #define SER_SPI1_BUS_TXINIT + #endif + + #ifndef SER_SPI1_BUS_TXCLOSE + /** + * Invoked after the last character has been transmitted. + * The default is no action. + */ + #define SER_SPI1_BUS_TXCLOSE + #endif +#endif +/*\}*/ + + /** * \def CONFIG_SER_STROBE * @@ -236,6 +226,13 @@ static unsigned char uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE]; static unsigned char uart1_txbuffer[CONFIG_UART1_TXBUFSIZE]; static unsigned char uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE]; +static unsigned char spi0_txbuffer[CONFIG_SPI0_TXBUFSIZE]; +static unsigned char spi0_rxbuffer[CONFIG_SPI0_RXBUFSIZE]; +#if CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7X256 +static unsigned char spi1_txbuffer[CONFIG_SPI1_TXBUFSIZE]; +static unsigned char spi1_rxbuffer[CONFIG_SPI1_RXBUFSIZE]; +#endif + /** * Internal hardware state structure * @@ -269,9 +266,17 @@ struct ArmSerial struct Serial *ser_uart0 = &ser_handles[SER_UART0]; struct Serial *ser_uart1 = &ser_handles[SER_UART1]; +struct Serial *ser_spi0 = &ser_handles[SER_SPI0]; +#if CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7X256 +struct Serial *ser_spi1 = &ser_handles[SER_SPI1]; +#endif static void uart0_irq_dispatcher(void); static void uart1_irq_dispatcher(void); +static void spi0_irq_handler(void); +#if CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7X256 +static void spi1_irq_handler(void); +#endif /* * Callbacks for USART0 */ @@ -279,8 +284,29 @@ static void uart0_init( UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct Serial *, ser)) { - SER_UART0_IRQ_INIT; + US0_IDR = 0xFFFFFFFF; + /* Set the vector. */ + AIC_SVR(US0_ID) = uart0_irq_dispatcher; + /* Initialize to edge triggered with defined priority. */ + AIC_SMR(US0_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED | SERIRQ_PRIORITY; + PMC_PCER = BV(US0_ID); + + /* + * - Reset USART0 + * - Set serial param: mode Normal, 8bit data, 1bit stop, parity none + * - Enable both the receiver and the transmitter + * - Enable only the RX complete interrupt + */ + US0_CR = BV(US_RSTRX) | BV(US_RSTTX); + US0_MR = US_CHMODE_NORMAL | US_CHRL_8 | US_NBSTOP_1 | US_PAR_NO; + US0_CR = BV(US_RXEN) | BV(US_TXEN); + US0_IER = BV(US_RXRDY); + SER_UART0_BUS_TXINIT; + + /* Enable the USART IRQ */ + AIC_IECR = BV(US0_ID); + SER_STROBE_INIT; } @@ -301,7 +327,12 @@ static void uart0_enabletxirq(struct SerialHardware *_hw) if (!hw->sending) { hw->sending = true; + /* + * - Enable the transmitter + * - Enable TX empty interrupt + */ SER_UART0_BUS_TXBEGIN; + US0_IER = BV(US_TXEMPTY); } } @@ -320,19 +351,19 @@ static void uart0_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity { case SER_PARITY_NONE: { - /* Parity mode. */ + /* Parity none. */ US0_MR |= US_PAR_NO; break; } case SER_PARITY_EVEN: { - /* Even parity.*/ + /* Even parity. */ US0_MR |= US_PAR_EVEN; break; } case SER_PARITY_ODD: { - /* Odd parity.*/ + /* Odd parity. */ US0_MR |= US_PAR_ODD; break; } @@ -348,8 +379,29 @@ static void uart1_init( UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct Serial *, ser)) { - SER_UART1_IRQ_INIT; + US1_IDR = 0xFFFFFFFF; + /* Set the vector. */ + AIC_SVR(US1_ID) = uart1_irq_dispatcher; + /* Initialize to edge triggered with defined priority. */ + AIC_SMR(US1_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED | SERIRQ_PRIORITY; + PMC_PCER = BV(US1_ID); + + /* + * - Reset USART1 + * - Set serial param: mode Normal, 8bit data, 1bit stop, parity none + * - Enable both the receiver and the transmitter + * - Enable only the RX complete interrupt + */ + US1_CR = BV(US_RSTRX) | BV(US_RSTTX); + US1_MR = US_CHMODE_NORMAL | US_CHRL_8 | US_NBSTOP_1 | US_PAR_NO; + US1_CR = BV(US_RXEN) | BV(US_TXEN); + US1_IER = BV(US_RXRDY); + SER_UART1_BUS_TXINIT; + + /* Enable the USART IRQ */ + AIC_IECR = BV(US1_ID); + SER_STROBE_INIT; } @@ -370,7 +422,12 @@ static void uart1_enabletxirq(struct SerialHardware *_hw) if (!hw->sending) { hw->sending = true; + /* + * - Enable the transmitter + * - Enable TX empty interrupt + */ SER_UART1_BUS_TXBEGIN; + US1_IER = BV(US_TXEMPTY); } } @@ -389,19 +446,19 @@ static void uart1_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity { case SER_PARITY_NONE: { - /* Parity mode. */ + /* Parity none. */ US1_MR |= US_PAR_NO; break; } case SER_PARITY_EVEN: { - /* Even parity.*/ + /* Even parity. */ US1_MR |= US_PAR_EVEN; break; } case SER_PARITY_ODD: { - /* Odd parity.*/ + /* Odd parity. */ US1_MR |= US_PAR_ODD; break; } @@ -411,6 +468,180 @@ static void uart1_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity } +/* SPI driver */ +static void spi0_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct Serial *, ser)) +{ + /* Disable PIO on SPI pins */ + PIOA_PDR = BV(SPI0_SPCK) | BV(SPI0_MOSI) | BV(SPI0_MISO); + + /* Reset device */ + SPI0_CR = BV(SPI_SWRST); + + /* + * Set SPI to master mode, fixed peripheral select, chip select directly connected to a peripheral device, + * SPI clock set to MCK, mode fault detection disabled, loopback disable, NPCS0 active, Delay between CS = 0 + */ + SPI0_MR = BV(SPI_MSTR) | BV(SPI_MODFDIS); + + /* + * Set SPI mode. + * At reset clock division factor is set to 0, that is + * *forbidden*. Set SPI clock to minimum to keep it valid. + */ + SPI0_CSR0 = BV(SPI_NCPHA) | (255 << SPI_SCBR_SHIFT); + + /* Disable all irqs */ + SPI0_IDR = 0xFFFFFFFF; + /* Set the vector. */ + AIC_SVR(SPI0_ID) = spi0_irq_handler; + /* Initialize to edge triggered with defined priority. */ + AIC_SMR(SPI0_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED | SERIRQ_PRIORITY; + /* Enable the USART IRQ */ + AIC_IECR = BV(SPI0_ID); + PMC_PCER = BV(SPI0_ID); + + /* Enable interrupt on tx buffer empty */ + SPI0_IER = BV(SPI_TXEMPTY); + + /* Enable SPI */ + SPI0_CR = BV(SPI_SPIEN); + + + SER_SPI0_BUS_TXINIT; + + SER_STROBE_INIT; +} + +static void spi0_cleanup(UNUSED_ARG(struct SerialHardware *, _hw)) +{ + /* Disable SPI */ + SPI0_CR = BV(SPI_SPIDIS); + + /* Disable all irqs */ + SPI0_IDR = 0xFFFFFFFF; + + SER_SPI0_BUS_TXCLOSE; + + /* Enable PIO on SPI pins */ + PIOA_PER = BV(SPI0_SPCK) | BV(SPI0_MOSI) | BV(SPI0_MISO); +} + +static void spi0_starttx(struct SerialHardware *_hw) +{ + struct ArmSerial *hw = (struct ArmSerial *)_hw; + + cpuflags_t flags; + IRQ_SAVE_DISABLE(flags); + + /* Send data only if the SPI is not already transmitting */ + if (!hw->sending && !fifo_isempty(&ser_spi0->txfifo)) + { + hw->sending = true; + SPI0_TDR = fifo_pop(&ser_spi0->txfifo); + } + + IRQ_RESTORE(flags); +} + +static void spi0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate) +{ + SPI0_CSR0 &= ~SPI_SCBR; + + ASSERT((uint8_t)DIV_ROUND(CLOCK_FREQ, rate)); + SPI0_CSR0 |= DIV_ROUND(CLOCK_FREQ, rate) << SPI_SCBR_SHIFT; +} + +#if CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7X256 +/* SPI driver */ +static void spi1_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct Serial *, ser)) +{ + /* Disable PIO on SPI pins */ + PIOA_PDR = BV(SPI1_SPCK) | BV(SPI1_MOSI) | BV(SPI1_MISO); + + /* Reset device */ + SPI1_CR = BV(SPI_SWRST); + +/* + * Set SPI to master mode, fixed peripheral select, chip select directly connected to a peripheral device, + * SPI clock set to MCK, mode fault detection disabled, loopback disable, NPCS0 active, Delay between CS = 0 + */ + SPI1_MR = BV(SPI_MSTR) | BV(SPI_MODFDIS); + + /* + * Set SPI mode. + * At reset clock division factor is set to 0, that is + * *forbidden*. Set SPI clock to minimum to keep it valid. + */ + SPI1_CSR0 = BV(SPI_NCPHA) | (255 << SPI_SCBR_SHIFT); + + /* Disable all irqs */ + SPI1_IDR = 0xFFFFFFFF; + /* Set the vector. */ + AIC_SVR(SPI1_ID) = spi1_irq_handler; + /* Initialize to edge triggered with defined priority. */ + AIC_SMR(SPI1_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED | SERIRQ_PRIORITY; + /* Enable the USART IRQ */ + AIC_IECR = BV(SPI1_ID); + PMC_PCER = BV(SPI1_ID); + + /* Enable interrupt on tx buffer empty */ + SPI1_IER = BV(SPI_TXEMPTY); + + /* Enable SPI */ + SPI1_CR = BV(SPI_SPIEN); + + + SER_SPI1_BUS_TXINIT; + + SER_STROBE_INIT; +} + +static void spi1_cleanup(UNUSED_ARG(struct SerialHardware *, _hw)) +{ + /* Disable SPI */ + SPI1_CR = BV(SPI_SPIDIS); + + /* Disable all irqs */ + SPI1_IDR = 0xFFFFFFFF; + + SER_SPI1_BUS_TXCLOSE; + + /* Enable PIO on SPI pins */ + PIOA_PER = BV(SPI1_SPCK) | BV(SPI1_MOSI) | BV(SPI1_MISO); +} + +static void spi1_starttx(struct SerialHardware *_hw) +{ + struct ArmSerial *hw = (struct ArmSerial *)_hw; + + cpuflags_t flags; + IRQ_SAVE_DISABLE(flags); + + /* Send data only if the SPI is not already transmitting */ + if (!hw->sending && !fifo_isempty(&ser_spi1->txfifo)) + { + hw->sending = true; + SPI1_TDR = fifo_pop(&ser_spi1->txfifo); + } + + IRQ_RESTORE(flags); +} + +static void spi1_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate) +{ + SPI1_CSR0 &= ~SPI_SCBR; + + ASSERT((uint8_t)DIV_ROUND(CLOCK_FREQ, rate)); + SPI1_CSR0 |= DIV_ROUND(CLOCK_FREQ, rate) << SPI_SCBR_SHIFT; +} +#endif + +static void spi_setparity(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(int, parity)) +{ + // nop +} + + static bool tx_sending(struct SerialHardware* _hw) { struct ArmSerial *hw = (struct ArmSerial *)_hw; @@ -450,6 +681,27 @@ static const struct SerialHardwareVT UART1_VT = C99INIT(txSending, tx_sending), }; +static const struct SerialHardwareVT SPI0_VT = +{ + C99INIT(init, spi0_init), + C99INIT(cleanup, spi0_cleanup), + C99INIT(setBaudrate, spi0_setbaudrate), + C99INIT(setParity, spi_setparity), + C99INIT(txStart, spi0_starttx), + C99INIT(txSending, tx_sending), +}; +#if CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7X128 +static const struct SerialHardwareVT SPI1_VT = +{ + C99INIT(init, spi1_init), + C99INIT(cleanup, spi1_cleanup), + C99INIT(setBaudrate, spi1_setbaudrate), + C99INIT(setParity, spi_setparity), + C99INIT(txStart, spi1_starttx), + C99INIT(txSending, tx_sending), +}; +#endif + static struct ArmSerial UARTDescs[SER_CNT] = { { @@ -471,7 +723,31 @@ static struct ArmSerial UARTDescs[SER_CNT] = C99INIT(rxbuffer_size, sizeof(uart1_rxbuffer)), }, C99INIT(sending, false), + }, + + { + C99INIT(hw, /**/) { + C99INIT(table, &SPI0_VT), + C99INIT(txbuffer, spi0_txbuffer), + C99INIT(rxbuffer, spi0_rxbuffer), + C99INIT(txbuffer_size, sizeof(spi0_txbuffer)), + C99INIT(rxbuffer_size, sizeof(spi0_rxbuffer)), + }, + C99INIT(sending, false), + }, + #if CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7X128 + { + C99INIT(hw, /**/) { + C99INIT(table, &SPI1_VT), + C99INIT(txbuffer, spi1_txbuffer), + C99INIT(rxbuffer, spi1_rxbuffer), + C99INIT(txbuffer_size, sizeof(spi1_txbuffer)), + C99INIT(rxbuffer_size, sizeof(spi1_rxbuffer)), + }, + C99INIT(sending, false), } + + #endif }; struct SerialHardware *ser_hw_getdesc(int unit) @@ -491,6 +767,10 @@ static void uart0_irq_tx(void) if (fifo_isempty(txfifo)) { + /* + * - Disable the TX empty interrupts + */ + US0_IDR = BV(US_TXEMPTY); SER_UART0_BUS_TXEND; UARTDescs[SER_UART0].sending = false; } @@ -527,18 +807,17 @@ static void uart0_irq_rx(void) /** * Serial IRQ dispatcher for USART0. */ -static void uart0_irq_dispatcher(void) __attribute__ ((naked)); +static void uart0_irq_dispatcher(void) __attribute__ ((interrupt)); static void uart0_irq_dispatcher(void) { - IRQ_ENTRY(); - - if (US0_IMR & BV(US_RXRDY)) + if (US0_CSR & BV(US_RXRDY)) uart0_irq_rx(); - if (US0_IMR & BV(US_TXRDY)) + if (US0_CSR & BV(US_TXEMPTY)) uart0_irq_tx(); - IRQ_EXIT(); + /* Inform hw that we have served the IRQ */ + AIC_EOICR = 0; } /** @@ -552,6 +831,10 @@ static void uart1_irq_tx(void) if (fifo_isempty(txfifo)) { + /* + * - Disable the TX empty interrupts + */ + US1_IDR = BV(US_TXEMPTY); SER_UART1_BUS_TXEND; UARTDescs[SER_UART1].sending = false; } @@ -588,16 +871,76 @@ static void uart1_irq_rx(void) /** * Serial IRQ dispatcher for USART1. */ -static void uart1_irq_dispatcher(void) __attribute__ ((naked)); +static void uart1_irq_dispatcher(void) __attribute__ ((interrupt)); static void uart1_irq_dispatcher(void) { - IRQ_ENTRY(); - - if (US1_IMR & BV(US_RXRDY)) + if (US1_CSR & BV(US_RXRDY)) uart1_irq_rx(); - if (US1_IMR & BV(US_TXRDY)) + if (US1_CSR & BV(US_TXEMPTY)) uart1_irq_tx(); - IRQ_EXIT(); + /* Inform hw that we have served the IRQ */ + AIC_EOICR = 0; } + +/** + * SPI0 interrupt handler + */ +static void spi0_irq_handler(void) __attribute__ ((interrupt)); +static void spi0_irq_handler(void) +{ + SER_STROBE_ON; + + char c = SPI0_RDR; + /* Read incoming byte. */ + if (!fifo_isfull(&ser_spi0->rxfifo)) + fifo_push(&ser_spi0->rxfifo, c); + /* + * FIXME + else + ser_spi0->status |= SERRF_RXFIFOOVERRUN; + */ + + /* Send */ + if (!fifo_isempty(&ser_spi0->txfifo)) + SPI0_TDR = fifo_pop(&ser_spi0->txfifo); + else + UARTDescs[SER_SPI0].sending = false; + + /* Inform hw that we have served the IRQ */ + AIC_EOICR = 0; + SER_STROBE_OFF; +} + + +#if CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7X128 +/** + * SPI1 interrupt handler + */ +static void spi1_irq_handler(void) __attribute__ ((interrupt)); +static void spi1_irq_handler(void) +{ + SER_STROBE_ON; + + char c = SPI1_RDR; + /* Read incoming byte. */ + if (!fifo_isfull(&ser_spi1->rxfifo)) + fifo_push(&ser_spi1->rxfifo, c); + /* + * FIXME + else + ser_spi1->status |= SERRF_RXFIFOOVERRUN; + */ + + /* Send */ + if (!fifo_isempty(&ser_spi1->txfifo)) + SPI1_TDR = fifo_pop(&ser_spi1->txfifo); + else + UARTDescs[SER_SPI1].sending = false; + + /* Inform hw that we have served the IRQ */ + AIC_EOICR = 0; + SER_STROBE_OFF; +} +#endif