X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=cpu%2Farm%2Fdrv%2Fser_at91.c;h=cef4c96fbc74e0cc6f9a2d7053a716ab68dc57e4;hb=6b98394f8b772c4e4d8784f1b810e7435ffe701a;hp=27f4c06bc1195fc92ea8cc7a223db5f5716aa5c2;hpb=8e08b9a36fe019fe1b86635425cab4f954852b39;p=bertos.git diff --git a/cpu/arm/drv/ser_at91.c b/cpu/arm/drv/ser_at91.c index 27f4c06b..cef4c96f 100644 --- a/cpu/arm/drv/ser_at91.c +++ b/cpu/arm/drv/ser_at91.c @@ -40,7 +40,7 @@ #include -//#include "ser_at91.h" +#include #include #include @@ -52,6 +52,7 @@ #include +#define SERIRQ_PRIORITY 4 ///< default priority for serial irqs. /** * \name Overridable serial bus hooks @@ -87,7 +88,7 @@ /* Set the vector. */ \ AIC_SVR(US0_ID) = uart0_irq_dispatcher; \ /* Initialize to edge triggered with defined priority. */ \ - AIC_SMR(US0_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED; \ + AIC_SMR(US0_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED | SERIRQ_PRIORITY; \ /* Enable the USART IRQ */ \ AIC_IECR = BV(US0_ID); \ PMC_PCER = BV(US0_ID); \ @@ -104,18 +105,16 @@ * - Enable both the receiver and the transmitter * - Enable only the RX complete interrupt */ - #if CPU_ARM_AT91 - #define SER_UART0_BUS_TXINIT do { \ - PIOA_PDR = BV(5) | BV(6);\ - US0_CR = BV(US_RSTRX) | BV(US_RSTTX); \ - US0_MR = US_CHMODE_NORMAL | US_CHRL_8 | US_NBSTOP_1; \ - US0_CR = BV(US_RXEN) | BV(US_TXEN); \ - US0_IER = BV(US_RXRDY); \ - } while (0) - /*#elif Add other ARM families here */ - #else - #error Unknown CPU + #if !CPU_ARM_AT91SAM7S256 + #warning Check USART0 pins! #endif + #define SER_UART0_BUS_TXINIT do { \ + PIOA_PDR = BV(RXD0) | BV(TXD0); \ + US0_CR = BV(US_RSTRX) | BV(US_RSTTX); \ + US0_MR = US_CHMODE_NORMAL | US_CHRL_8 | US_NBSTOP_1; \ + US0_CR = BV(US_RXEN) | BV(US_TXEN); \ + US0_IER = BV(US_RXRDY); \ + } while (0) #endif @@ -137,7 +136,7 @@ * Invoked to send one character. */ #define SER_UART0_BUS_TXCHAR(c) do { \ - US0_THR = c; \ + US0_THR = (c); \ } while (0) #endif @@ -163,9 +162,9 @@ #define SER_UART1_IRQ_INIT do { \ US1_IDR = 0xFFFFFFFF; \ /* Set the vector. */ \ - AIC_SVR(US1_ID) = uart0_irq_dispatcher; \ + AIC_SVR(US1_ID) = uart1_irq_dispatcher; \ /* Initialize to edge triggered with defined priority. */ \ - AIC_SMR(US1_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED; \ + AIC_SMR(US1_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED | SERIRQ_PRIORITY; \ /* Enable the USART IRQ */ \ AIC_IECR = BV(US1_ID); \ PMC_PCER = BV(US1_ID); \ @@ -174,19 +173,16 @@ #ifndef SER_UART1_BUS_TXINIT /** \sa SER_UART1_BUS_TXINIT */ - #if CPU_ARM_AT91 - #define SER_UART1_BUS_TXINIT do { \ - PIOA_PDR = BV(0) | BV(1); \ - US1_CR = BV(US_RSTRX) | BV(US_RSTTX); \ - US1_MR = US_CHMODE_NORMAL | US_CHRL_8 | US_NBSTOP_1; \ - US1_CR = BV(US_RXEN) | BV(US_TXEN); \ - US1_IER = BV(US_RXRDY); \ - } while (0) - /*#elif Add other ARM families here */ - #else - #error Unknown CPU + #if !CPU_ARM_AT91SAM7S256 + #warning Check USART1 pins! #endif - + #define SER_UART1_BUS_TXINIT do { \ + PIOA_PDR = BV(RXD1) | BV(TXD1); \ + US1_CR = BV(US_RSTRX) | BV(US_RSTTX); \ + US1_MR = US_CHMODE_NORMAL | US_CHRL_8 | US_NBSTOP_1; \ + US1_CR = BV(US_RXEN) | BV(US_TXEN); \ + US1_IER = BV(US_RXRDY); \ + } while (0) #endif #ifndef SER_UART1_BUS_TXBEGIN @@ -200,7 +196,7 @@ #ifndef SER_UART1_BUS_TXCHAR /** \sa SER_UART1_BUS_TXCHAR */ #define SER_UART1_BUS_TXCHAR(c) do { \ - US1_THR = c; \ + US1_THR = (c); \ } while (0) #endif @@ -213,6 +209,33 @@ } while (0) #endif +#if 0 +/** + * \name Overridable SPI hooks + * + * These can be redefined in hw.h to implement + * special bus policies such as slave select pin handling, etc. + * + * \{ + */ +#ifndef SER_SPI_BUS_TXINIT + /** + * Default TXINIT macro - invoked in spi_init() + * The default is no action. + */ + #define SER_SPI_BUS_TXINIT +#endif + +#ifndef SER_SPI_BUS_TXCLOSE + /** + * Invoked after the last character has been transmitted. + * The default is no action. + */ + #define SER_SPI_BUS_TXCLOSE +#endif +/*\}*/ +#endif + /** * \def CONFIG_SER_STROBE * @@ -240,6 +263,11 @@ static unsigned char uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE]; static unsigned char uart1_txbuffer[CONFIG_UART1_TXBUFSIZE]; static unsigned char uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE]; +#if 0 +static unsigned char spi_txbuffer[CONFIG_SPI_TXBUFSIZE]; +static unsigned char spi_rxbuffer[CONFIG_SPI_RXBUFSIZE]; +#endif + /** * Internal hardware state structure * @@ -273,141 +301,12 @@ struct ArmSerial struct Serial *ser_uart0 = &ser_handles[SER_UART0]; struct Serial *ser_uart1 = &ser_handles[SER_UART1]; -/** - * Serial 0 TX interrupt handler - */ -static void usart0_irq_tx(void) -{ - SER_STROBE_ON; - - struct FIFOBuffer * const txfifo = &ser_uart0->txfifo; - - if (fifo_isempty(txfifo)) - { - SER_UART0_BUS_TXEND; - } - else - { - char c = fifo_pop(txfifo); -// kprintf("USART0 tx char: %c\n", c); - SER_UART0_BUS_TXCHAR(c); - } - - SER_STROBE_OFF; -} - -/** - * Serial 0 RX complete interrupt handler. - */ -static void usart0_irq_rx(void) -{ - SER_STROBE_ON; - - /* Should be read before US_CRS */ - ser_uart0->status |= US0_CSR & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR); - - char c = US0_RHR; - struct FIFOBuffer * const rxfifo = &ser_uart0->rxfifo; - - if (fifo_isfull(rxfifo)) - ser_uart0->status |= SERRF_RXFIFOOVERRUN; - else - { -// kprintf("USART0 recv char: %c\n", c); - fifo_push(rxfifo, c); - } - - SER_STROBE_OFF; -} - -/** - * Serial IRQ dispatcher for USART0. - */ -static void uart0_irq_dispatcher(void) __attribute__ ((naked)); -static void uart0_irq_dispatcher(void) -{ - IRQ_ENTRY(); - - if (US0_IMR & BV(US_RXRDY)) - { -// kprintf("IRQ RX USART0\n"); - usart0_irq_rx(); - } - if (US0_IMR & BV(US_TXRDY)) - { -// kprintf("IRQ TX USART0\n"); - usart0_irq_tx(); - } - IRQ_EXIT(); -} - -/** - * Serial 1 TX interrupt handler - */ -static void usart1_irq_tx(void) -{ - SER_STROBE_ON; - - struct FIFOBuffer * const txfifo = &ser_uart1->txfifo; - - if (fifo_isempty(txfifo)) - { - SER_UART1_BUS_TXEND; - } - else - { - char c = fifo_pop(txfifo); -// kprintf("USART1 tx char: %c\n", c); - SER_UART1_BUS_TXCHAR(c); - } - - SER_STROBE_OFF; -} - -/** - * Serial 1 RX complete interrupt handler. - */ -static void usart1_irq_rx(void) -{ - SER_STROBE_ON; - - /* Should be read before US_CRS */ - ser_uart1->status |= US1_CSR & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR); - - char c = US1_RHR; - struct FIFOBuffer * const rxfifo = &ser_uart1->rxfifo; - - if (fifo_isfull(rxfifo)) - ser_uart1->status |= SERRF_RXFIFOOVERRUN; - else - { -// kprintf("USART1 recv char: %c\n", c); - fifo_push(rxfifo, c); - } - - SER_STROBE_OFF; -} - -/** - * Serial IRQ dispatcher for USART1. - */ -static void uart1_irq_dispatcher(void) __attribute__ ((naked)); -static void uart1_irq_dispatcher(void) -{ - IRQ_ENTRY(); +#if 0 +struct Serial *ser_spi = &ser_handles[SER_SPI]; +#endif - if (US1_IMR & BV(US_RXRDY)) - { -// kprintf("IRQ RX USART1\n"); - usart1_irq_rx(); - } - if (US1_IMR & BV(US_TXRDY)) - { -// kprintf("IRQ TX USART1\n"); - usart1_irq_tx(); - } - IRQ_EXIT(); -} +static void uart0_irq_dispatcher(void); +static void uart1_irq_dispatcher(void); /* * Callbacks for USART0 */ @@ -450,13 +349,14 @@ static void uart0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned static void uart0_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity) { + US0_MR &= ~US_PAR_MASK; /* Set UART parity */ switch(parity) { case SER_PARITY_NONE: { /* Parity mode. */ - US0_MR |= US_PAR_MASK; + US0_MR |= US_PAR_NO; break; } case SER_PARITY_EVEN: @@ -471,6 +371,8 @@ static void uart0_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity US0_MR |= US_PAR_ODD; break; } + default: + ASSERT(0); } } @@ -510,19 +412,20 @@ static void uart1_enabletxirq(struct SerialHardware *_hw) static void uart1_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate) { /* Compute baud-rate period */ - US0_BRGR = CLOCK_FREQ / (16 * rate); + US1_BRGR = CLOCK_FREQ / (16 * rate); //DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);) } static void uart1_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity) { + US1_MR &= ~US_PAR_MASK; /* Set UART parity */ switch(parity) { case SER_PARITY_NONE: { /* Parity mode. */ - US1_MR |= US_PAR_MASK; + US1_MR |= US_PAR_NO; break; } case SER_PARITY_EVEN: @@ -537,9 +440,128 @@ static void uart1_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity US1_MR |= US_PAR_ODD; break; } + default: + ASSERT(0); + } + +} + +/* SPI driver */ +#if 0 +static void spi_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct Serial *, ser)) +{ + /* + * Set MOSI and SCK ports out, MISO in. + * + * The ATmega64/128 datasheet explicitly states that the input/output + * state of the SPI pins is not significant, as when the SPI is + * active the I/O port are overrided. + * This is *blatantly FALSE*. + * + * Moreover, the MISO pin on the board_kc *must* be in high impedance + * state even when the SPI is off, because the line is wired together + * with the KBus serial RX, and the transmitter of the slave boards + * would be unable to drive the line. + */ + ATOMIC(SPI_DDR |= (BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT))); + + /* + * If the SPI master mode is activated and the SS pin is in input and tied low, + * the SPI hardware will automatically switch to slave mode! + * For proper communication this pins should therefore be: + * - as output + * - as input but tied high forever! + * This driver set the pin as output. + */ + #warning SPI SS pin set as output for proper operation, check schematics for possible conflicts. + ATOMIC(SPI_DDR |= BV(SPI_SS_BIT)); + + ATOMIC(SPI_DDR &= ~BV(SPI_MISO_BIT)); + /* Enable SPI, IRQ on, Master */ + SPCR = BV(SPE) | BV(SPIE) | BV(MSTR); + + /* Set data order */ + #if CONFIG_SPI_DATA_ORDER == SER_LSB_FIRST + SPCR |= BV(DORD); + #endif + + /* Set SPI clock rate */ + #if CONFIG_SPI_CLOCK_DIV == 128 + SPCR |= (BV(SPR1) | BV(SPR0)); + #elif (CONFIG_SPI_CLOCK_DIV == 64 || CONFIG_SPI_CLOCK_DIV == 32) + SPCR |= BV(SPR1); + #elif (CONFIG_SPI_CLOCK_DIV == 16 || CONFIG_SPI_CLOCK_DIV == 8) + SPCR |= BV(SPR0); + #elif (CONFIG_SPI_CLOCK_DIV == 4 || CONFIG_SPI_CLOCK_DIV == 2) + // SPR0 & SDPR1 both at 0 + #else + #error Unsupported SPI clock division factor. + #endif + + /* Set SPI2X bit (spi double frequency) */ + #if (CONFIG_SPI_CLOCK_DIV == 128 || CONFIG_SPI_CLOCK_DIV == 64 \ + || CONFIG_SPI_CLOCK_DIV == 16 || CONFIG_SPI_CLOCK_DIV == 4) + SPSR &= ~BV(SPI2X); + #elif (CONFIG_SPI_CLOCK_DIV == 32 || CONFIG_SPI_CLOCK_DIV == 8 || CONFIG_SPI_CLOCK_DIV == 2) + SPSR |= BV(SPI2X); + #else + #error Unsupported SPI clock division factor. + #endif + + /* Set clock polarity */ + #if CONFIG_SPI_CLOCK_POL == 1 + SPCR |= BV(CPOL); + #endif + + /* Set clock phase */ + #if CONFIG_SPI_CLOCK_PHASE == 1 + SPCR |= BV(CPHA); + #endif + SER_SPI_BUS_TXINIT; + + SER_STROBE_INIT; +} + +static void spi_cleanup(UNUSED_ARG(struct SerialHardware *, _hw)) +{ + SPCR = 0; + + SER_SPI_BUS_TXCLOSE; + + /* Set all pins as inputs */ + ATOMIC(SPI_DDR &= ~(BV(SPI_MISO_BIT) | BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT) | BV(SPI_SS_BIT))); +} + +static void spi_starttx(struct SerialHardware *_hw) +{ + struct AvrSerial *hw = (struct AvrSerial *)_hw; + + cpuflags_t flags; + IRQ_SAVE_DISABLE(flags); + + /* Send data only if the SPI is not already transmitting */ + if (!hw->sending && !fifo_isempty(&ser_spi->txfifo)) + { + hw->sending = true; + SPDR = fifo_pop(&ser_spi->txfifo); } + IRQ_RESTORE(flags); +} + +static void spi_setbaudrate( + UNUSED_ARG(struct SerialHardware *, _hw), + UNUSED_ARG(unsigned long, rate)) +{ + // nop +} + +static void spi_setparity(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(int, parity)) +{ + // nop } +#endif + static bool tx_sending(struct SerialHardware* _hw) { @@ -572,14 +594,26 @@ static const struct SerialHardwareVT UART0_VT = static const struct SerialHardwareVT UART1_VT = { - C99INIT(init, uart0_init), - C99INIT(cleanup, uart0_cleanup), - C99INIT(setBaudrate, uart0_setbaudrate), - C99INIT(setParity, uart0_setparity), - C99INIT(txStart, uart0_enabletxirq), + C99INIT(init, uart1_init), + C99INIT(cleanup, uart1_cleanup), + C99INIT(setBaudrate, uart1_setbaudrate), + C99INIT(setParity, uart1_setparity), + C99INIT(txStart, uart1_enabletxirq), C99INIT(txSending, tx_sending), }; +#if 0 +static const struct SerialHardwareVT SPI_VT = +{ + C99INIT(init, spi_init), + C99INIT(cleanup, spi_cleanup), + C99INIT(setBaudrate, spi_setbaudrate), + C99INIT(setParity, spi_setparity), + C99INIT(txStart, spi_starttx), + C99INIT(txSending, tx_sending), +}; +#endif + static struct ArmSerial UARTDescs[SER_CNT] = { { @@ -601,7 +635,19 @@ static struct ArmSerial UARTDescs[SER_CNT] = C99INIT(rxbuffer_size, sizeof(uart1_rxbuffer)), }, C99INIT(sending, false), + }, +#if 0 + { + C99INIT(hw, /**/) { + C99INIT(table, &SPI_VT), + C99INIT(txbuffer, spi_txbuffer), + C99INIT(rxbuffer, spi_rxbuffer), + C99INIT(txbuffer_size, sizeof(spi_txbuffer)), + C99INIT(rxbuffer_size, sizeof(spi_rxbuffer)), + }, + C99INIT(sending, false), } +#endif }; struct SerialHardware *ser_hw_getdesc(int unit) @@ -609,3 +655,125 @@ struct SerialHardware *ser_hw_getdesc(int unit) ASSERT(unit < SER_CNT); return &UARTDescs[unit].hw; } + +/** + * Serial 0 TX interrupt handler + */ +static void uart0_irq_tx(void) +{ + SER_STROBE_ON; + + struct FIFOBuffer * const txfifo = &ser_uart0->txfifo; + + if (fifo_isempty(txfifo)) + { + SER_UART0_BUS_TXEND; + UARTDescs[SER_UART0].sending = false; + } + else + { + char c = fifo_pop(txfifo); + SER_UART0_BUS_TXCHAR(c); + } + + SER_STROBE_OFF; +} + +/** + * Serial 0 RX complete interrupt handler. + */ +static void uart0_irq_rx(void) +{ + SER_STROBE_ON; + + /* Should be read before US_CRS */ + ser_uart0->status |= US0_CSR & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR); + + char c = US0_RHR; + struct FIFOBuffer * const rxfifo = &ser_uart0->rxfifo; + + if (fifo_isfull(rxfifo)) + ser_uart0->status |= SERRF_RXFIFOOVERRUN; + else + fifo_push(rxfifo, c); + + SER_STROBE_OFF; +} + +/** + * Serial IRQ dispatcher for USART0. + */ +static void uart0_irq_dispatcher(void) __attribute__ ((naked)); +static void uart0_irq_dispatcher(void) +{ + IRQ_ENTRY(); + + if (US0_IMR & BV(US_RXRDY)) + uart0_irq_rx(); + + if (US0_IMR & BV(US_TXRDY)) + uart0_irq_tx(); + + IRQ_EXIT(); +} + +/** + * Serial 1 TX interrupt handler + */ +static void uart1_irq_tx(void) +{ + SER_STROBE_ON; + + struct FIFOBuffer * const txfifo = &ser_uart1->txfifo; + + if (fifo_isempty(txfifo)) + { + SER_UART1_BUS_TXEND; + UARTDescs[SER_UART1].sending = false; + } + else + { + char c = fifo_pop(txfifo); + SER_UART1_BUS_TXCHAR(c); + } + + SER_STROBE_OFF; +} + +/** + * Serial 1 RX complete interrupt handler. + */ +static void uart1_irq_rx(void) +{ + SER_STROBE_ON; + + /* Should be read before US_CRS */ + ser_uart1->status |= US1_CSR & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR); + + char c = US1_RHR; + struct FIFOBuffer * const rxfifo = &ser_uart1->rxfifo; + + if (fifo_isfull(rxfifo)) + ser_uart1->status |= SERRF_RXFIFOOVERRUN; + else + fifo_push(rxfifo, c); + + SER_STROBE_OFF; +} + +/** + * Serial IRQ dispatcher for USART1. + */ +static void uart1_irq_dispatcher(void) __attribute__ ((naked)); +static void uart1_irq_dispatcher(void) +{ + IRQ_ENTRY(); + + if (US1_IMR & BV(US_RXRDY)) + uart1_irq_rx(); + + if (US1_IMR & BV(US_TXRDY)) + uart1_irq_tx(); + + IRQ_EXIT(); +}