X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=cpu%2Farm%2Fio%2Fat91_tc.h;h=080d58813ab761884320d65c0f7b7220bd804f80;hb=4f8d7e21683129063caec365f37e9a90501c3891;hp=5a9772eb2d42d61e1669888d589d8573878e3dfb;hpb=80a7f29525ac68106aec85dec0b3b4a12a75b31e;p=bertos.git

diff --git a/cpu/arm/io/at91_tc.h b/cpu/arm/io/at91_tc.h
index 5a9772eb..080d5881 100644
--- a/cpu/arm/io/at91_tc.h
+++ b/cpu/arm/io/at91_tc.h
@@ -269,9 +269,9 @@
 #define TC2_IDR        (*((reg32_t *)(TC_BASE + TC_TC2_OFF + TC_IDR_OFF))) ///< Channel 2 interrupt disable register address.
 
 #define TC_IMR_OFF              0x0000002C      ///< Interrupt Mask Register offset.
-#define TC0_IMR        (*((reg32_t *)(TC_BASE + TC_TC0_OFF + TC_SR_OFF))) ///< Channel 0 interrupt mask register address.
-#define TC1_IMR        (*((reg32_t *)(TC_BASE + TC_TC1_OFF + TC_SR_OFF))) ///< Channel 1 interrupt mask register address.
-#define TC2_IMR        (*((reg32_t *)(TC_BASE + TC_TC2_OFF + TC_SR_OFF))) ///< Channel 2 interrupt mask register address.
+#define TC0_IMR        (*((reg32_t *)(TC_BASE + TC_TC0_OFF + TC_IMR_OFF))) ///< Channel 0 interrupt mask register address.
+#define TC1_IMR        (*((reg32_t *)(TC_BASE + TC_TC1_OFF + TC_IMR_OFF))) ///< Channel 1 interrupt mask register address.
+#define TC2_IMR        (*((reg32_t *)(TC_BASE + TC_TC2_OFF + TC_IMR_OFF))) ///< Channel 2 interrupt mask register address.
 
 #define TC_COVFS                         0      ///< Counter overflow flag.
 #define TC_LOVRS                         1      ///< Load overrun flag.