X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=cpu%2Farm%2Fio%2Fat91sam7.h;h=84ddfed2733d2975b2091bc6645a28d81ff45424;hb=cdf0c088714fe7b9ee7e10b94858d8eff41f7899;hp=f91690e82fa05b3c7c1673353dfe981b89f36024;hpb=3d3ba5cae20af3f5d1a75d7a3d727a2199160137;p=bertos.git

diff --git a/cpu/arm/io/at91sam7.h b/cpu/arm/io/at91sam7.h
index f91690e8..84ddfed2 100644
--- a/cpu/arm/io/at91sam7.h
+++ b/cpu/arm/io/at91sam7.h
@@ -76,7 +76,7 @@
 
 #include <cfg/compiler.h>
 
-#if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7S256
+#if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7S256
 	#define FLASH_BASE      0x100000UL
 	#define RAM_BASE        0x200000UL
 
@@ -100,7 +100,7 @@
 	#define VREG_BASE       0xFFFFFD60      ///< Voltage regulator mode controller base address.
 	#define MC_BASE         0xFFFFFF00      ///< Memory controller base.
 
-	#if CPU_ARM_AT91SAM7X256
+	#if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128
 		#define CAN_BASE        0xFFFD0000      ///< PWM controller base address.
 		#define EMAC_BASE       0xFFFDC000      ///< Ethernet MAC address.
 		#define SPI0_BASE       0xFFFE0000      ///< SPI0 base address.
@@ -136,13 +136,14 @@
 #include "at91_pio.h"
 #include "at91_us.h"
 #include "at91_dbgu.h"
+#include "at91_tc.h"
 //TODO: add other peripherals
 
 /**
  * Peripheral Identifiers and Interrupts
  *\{
  */
-#if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7S256
+#if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7S256 || CPU_ARM_AT91SAM7X128
 	#define FIQ_ID      0       ///< Fast interrupt ID.
 	#define SYSC_ID     1       ///< System controller interrupt.
 	#define US0_ID      6       ///< USART 0 ID.
@@ -158,7 +159,7 @@
 	#define IRQ0_ID     30      ///< External interrupt 0 ID.
 	#define IRQ1_ID     31      ///< External interrupt 1 ID.
 
-	#if CPU_ARM_AT91SAM7X256
+	#if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128
 		#define PIOA_ID     2       ///< Parallel A I/O controller ID.
 		#define PIOB_ID     3       ///< Parallel B I/O controller ID.
 		#define SPI0_ID     4       ///< Serial peripheral interface 0 ID.
@@ -185,7 +186,7 @@
 /*\}*/
 
 /**
- * USART pins name
+ * USART & DEBUG pin names
  *\{
  */
 #if CPU_ARM_AT91SAM7S256
@@ -193,16 +194,17 @@
 	#define TXD0        6
 	#define RXD1       21
 	#define TXD1       22
-
-#elif CPU_ARM_AT91SAM7X256
-	#define RXD0       0 // PA0
-	#define TXD0       1 // PA1
-	#define RXD1       5 // PA5
-	#define TXD1       6 // PA6
-
+	#define DTXD       10
+	#define DRXD        9
+#elif CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128
+	#define RXD0        0 // PA0
+	#define TXD0        1 // PA1
+	#define RXD1        5 // PA5
+	#define TXD1        6 // PA6
+	#define DTXD       28 // PA28
+	#define DRXD       27 // PA27
 #else
-	#error No USART pins name definition for selected ARM CPU
-
+	#error No USART & debug pin names definition for selected ARM CPU
 #endif
 /*\}*/
 
@@ -216,7 +218,7 @@
 	#define MOSI       13
 	#define SPCK       14
 
-#elif CPU_ARM_AT91SAM7X256
+#elif CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128
 	#define SPI0_NPCS0  12 // Same as NSS pin. PA12
 	#define SPI0_NPCS1  13 // PA13
 	#define SPI0_NPCS2  14 // PA14
@@ -239,4 +241,22 @@
 #endif
 /*\}*/
 
+/**
+ * Timer counter pins definition.
+ *\{
+ */
+#if CPU_ARM_AT91SAM7X256
+	#define TIOA0  23 // PB23
+	#define TIOB0  24 // PB24
+	#define TIOA1  25 // PB25
+	#define TIOB1  26 // PB26
+	#define TIOA2  27 // PB27
+	#define TIOB2  28 // PB28
+
+#else
+	#error No Timer Conter pin names definition for selected ARM CPU
+
+#endif
+/*\}*/
+
 #endif /* AT91SAM7_H */