X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=cpu%2Fattr.h;h=302b38c987089043a0ac7b2f8deabb6342b4f4bd;hb=633a26b43c6a9a43ecb1d08425fbb53145e10bc1;hp=678eac68287f010ea70002a962f8cc115a4fc9e1;hpb=efbdba7e2814415234ef47bd10ff888559ea90af;p=bertos.git diff --git a/cpu/attr.h b/cpu/attr.h index 678eac68..302b38c9 100644 --- a/cpu/attr.h +++ b/cpu/attr.h @@ -102,13 +102,23 @@ #define CPU_SAVED_REGS_CNT 9 #define CPU_STACK_GROWS_UPWARD 0 #define CPU_SP_ON_EMPTY_SLOT 0 - #define CPU_BYTE_ORDER (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN) #define CPU_HARVARD 0 #ifdef __IAR_SYSTEMS_ICC__ - #define NOP __no_operation() + #warning Check CPU_BYTE_ORDER + #define CPU_BYTE_ORDER (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN) + + #define NOP __no_operation() #else /* !__IAR_SYSTEMS_ICC__ */ - #define NOP asm volatile ("mov r0,r0" ::) + #if defined(__ARMEB__) + #define CPU_BYTE_ORDER CPU_BIG_ENDIAN + #elif defined(__ARMEL__) + #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN + #else + #error Unable to detect ARM endianness! + #endif + + #define NOP asm volatile ("mov r0,r0" ::) /** * Initialization value for registers in stack frame. @@ -256,6 +266,30 @@ CPU_PUSH_WORD((sp), funcaddr>>8); \ } while (0) + /* + * If the kernel is in idle-spinning, the processor executes: + * + * IRQ_ENABLE; + * CPU_IDLE; + * IRQ_DISABLE; + * + * IRQ_ENABLE is translated in asm as "sei" and IRQ_DISABLE as "cli". + * We could define CPU_IDLE to expand to none, so the resulting + * asm code would be: + * + * sei; + * cli; + * + * But Atmel datasheet states: + * "When using the SEI instruction to enable interrupts, + * the instruction following SEI will be executed *before* + * any pending interrupts", so "cli" is executed before any + * pending interrupt with the result that IRQs will *NOT* + * be enabled! + * To ensure that IRQ will run a NOP is required. + */ + #define CPU_IDLE NOP + #else #define CPU_PUSH_CALL_CONTEXT(sp, func) \ CPU_PUSH_WORD((sp), (cpustack_t)(func))