X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=cpu%2Fattr.h;h=ce6e4ae38d35823c5b083860b97ff1c2ad5cf66a;hb=f3ba158c1ebfcef6c85759056d0a3d5f421ea870;hp=678eac68287f010ea70002a962f8cc115a4fc9e1;hpb=efbdba7e2814415234ef47bd10ff888559ea90af;p=bertos.git

diff --git a/cpu/attr.h b/cpu/attr.h
index 678eac68..ce6e4ae3 100644
--- a/cpu/attr.h
+++ b/cpu/attr.h
@@ -45,6 +45,7 @@
 #include <cfg/compiler.h> /* for uintXX_t */
 #include <cfg/arch_config.h>  /* ARCH_EMUL */
 
+#include "appconfig.h" // CONFIG_FAST_MEM
 
 /**
  * \name Macros for determining CPU endianness.
@@ -102,13 +103,25 @@
 	#define CPU_SAVED_REGS_CNT     9
 	#define CPU_STACK_GROWS_UPWARD 0
 	#define CPU_SP_ON_EMPTY_SLOT   0
-	#define CPU_BYTE_ORDER         (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN)
 	#define CPU_HARVARD            0
 
 	#ifdef __IAR_SYSTEMS_ICC__
-		#define NOP         __no_operation()
-	#else /* !__IAR_SYSTEMS_ICC__ */
-		#define NOP         asm volatile ("mov r0,r0" ::)
+		#warning Check CPU_BYTE_ORDER
+		#define CPU_BYTE_ORDER (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN)
+
+		#define NOP            __no_operation()
+
+	#else /* GCC and compatibles */
+
+		#if defined(__ARMEB__)
+  			#define CPU_BYTE_ORDER CPU_BIG_ENDIAN
+  		#elif defined(__ARMEL__)
+  			#define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
+		#else
+			#error Unable to detect ARM endianness!
+  		#endif
+
+		#define NOP            asm volatile ("mov r0,r0" ::)
 
 		/**
 	 	 * Initialization value for registers in stack frame.
@@ -124,6 +137,34 @@
 	 	 */
 		#define CPU_REG_INIT_VALUE(reg) (reg == (CPU_SAVED_REGS_CNT - 1) ? 0x13 : 0)
 
+		#if CONFIG_FAST_MEM
+			/**
+			 * Function attribute for use with performance critical code.
+			 *
+			 * On the AT91 family, code residing in flash has wait states.
+			 * Moving functions to the data section is a quick & dirty way
+			 * to get them transparently copied to SRAM for zero-wait-state
+			 * operation.
+			 */
+			#define FAST_FUNC __attribute__((section(".data")))
+
+			/**
+			 * Data attribute to move constant data to fast memory storage.
+			 *
+			 * \see FAST_FUNC
+			 */
+			#define FAST_RODATA __attribute__((section(".data")))
+
+		#else // !CONFIG_FAST_MEM
+			#define FAST_RODATA /**/
+			#define FAST_FUNC /**/
+		#endif
+
+		/**
+		 * Function attribute to declare an interrupt service routine.
+		 */
+		#define ISR_FUNC __attribute__((interrupt))
+
 	#endif /* !__IAR_SYSTEMS_ICC_ */
 
 #elif CPU_PPC
@@ -256,6 +297,30 @@
 			CPU_PUSH_WORD((sp), funcaddr>>8); \
 		} while (0)
 
+	/*
+	 * If the kernel is in idle-spinning, the processor executes:
+	 *
+	 * IRQ_ENABLE;
+	 * CPU_IDLE;
+	 * IRQ_DISABLE;
+	 *
+	 * IRQ_ENABLE is translated in asm as "sei" and IRQ_DISABLE as "cli".
+	 * We could define CPU_IDLE to expand to none, so the resulting
+	 * asm code would be:
+	 *
+	 * sei;
+	 * cli;
+	 *
+	 * But Atmel datasheet states:
+	 * "When using the SEI instruction to enable interrupts,
+	 * the instruction following SEI will be executed *before*
+	 * any pending interrupts", so "cli" is executed before any
+	 * pending interrupt with the result that IRQs will *NOT*
+	 * be enabled!
+	 * To ensure that IRQ will run a NOP is required.
+	 */
+	#define CPU_IDLE NOP
+
 #else
 	#define CPU_PUSH_CALL_CONTEXT(sp, func) \
 		CPU_PUSH_WORD((sp), (cpustack_t)(func))