X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=cpu%2Fcpu.h;h=03a0827df5cf9d7518c772e997edb3f60fedcc19;hb=0ace0d776cdbb34ed7f4aaa0815d4e2dd46fcec7;hp=a99285dc19746e24dfb4c625872fdcfd7f977ce2;hpb=df330fe6711957e5fb0434b8b7147d1edc05e414;p=bertos.git

diff --git a/cpu/cpu.h b/cpu/cpu.h
index a99285dc..03a0827d 100644
--- a/cpu/cpu.h
+++ b/cpu/cpu.h
@@ -26,7 +26,7 @@
  * invalidate any other reasons why the executable file might be covered by
  * the GNU General Public License.
  *
- * Copyright 2004, 2005,2006, 2007 Develer S.r.l. (http://www.develer.com/)
+ * Copyright 2004, 2005, 2006, 2007 Develer S.r.l. (http://www.develer.com/)
  * Copyright 2004 Giovanni Bajo
  *
  * -->
@@ -42,7 +42,6 @@
 #define CPU_CPU_H
 
 #include "detect.h"
-
 #include <cfg/compiler.h> /* for uintXX_t */
 #include <cfg/arch_config.h>  /* ARCH_EMUL */
 
@@ -56,10 +55,10 @@
 /*\}*/
 
 /** Macro to include cpu-specific versions of the headers. */
-#define CPU_HEADER(module)          PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).h)
+#define CPU_HEADER(module)          PP_STRINGIZE(drv/PP_CAT3(module, _, CPU_ID).h)
 
 /** Macro to include cpu-specific versions of implementation files. */
-#define CPU_CSOURCE(module)         PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).c)
+#define CPU_CSOURCE(module)         PP_STRINGIZE(drv/PP_CAT3(module, _, CPU_ID).c)
 
 
 #if CPU_I196
@@ -121,7 +120,7 @@
 	/* Register counts include SREG too */
 	#define CPU_REG_BITS           32
 	#define CPU_REGS_CNT           16
-	#define CPU_SAVED_REGS_CNT     FIXME
+	#define CPU_SAVED_REGS_CNT     9
 	#define CPU_STACK_GROWS_UPWARD 0
 	#define CPU_SP_ON_EMPTY_SLOT   0
 	#define CPU_BYTE_ORDER         (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN)
@@ -161,7 +160,6 @@
 		#define BREAKPOINT  /* asm("bkpt 0") DOES NOT WORK */
 
 	#else /* !__IAR_SYSTEMS_ICC__ */
-
 		#define NOP         asm volatile ("mov r0,r0" ::)
 
 		#define IRQ_DISABLE \
@@ -205,17 +203,33 @@
 			); \
 		} while (0)
 
-		#define IRQ_GETSTATE() \
+		#define CPU_READ_FLAGS() \
 		({ \
-			uint32_t sreg; \
+			cpuflags_t sreg; \
 			asm volatile ( \
 				"mrs %0, cpsr\n\t" \
 				: "=r" (sreg) \
 				: /* no inputs */ \
 			); \
-			!((sreg & 0xc0) == 0xc0); \
+			sreg; \
 		})
 
+		#define IRQ_GETSTATE() (!((CPU_READ_FLAGS() & 0xc0) == 0xc0))
+
+		/**
+	 	 * Initialization value for registers in stack frame.
+	 	 * The register index is not directly corrispondent to CPU
+	 	 * register numbers, but is related to how are pushed to
+	 	 * stack (\see asm_switch_context).
+		 * Index (CPU_SAVED_REGS_CNT - 1) is the CPSR register,
+		 * the initial value is set to:
+		 * - All flags (N, Z, C, V) set to 0.
+		 * - IRQ and FIQ enabled.
+		 * - ARM state.
+		 * - CPU in Supervisor Mode (SVC).
+	 	 */
+		#define CPU_REG_INIT_VALUE(reg) (reg == (CPU_SAVED_REGS_CNT - 1) ? 0x13 : 0)
+
 	#endif /* !__IAR_SYSTEMS_ICC_ */
 
 #elif CPU_PPC