X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=cpu.h;h=1c8a62f387df5f85d449142958f491d09b84ce8d;hb=6f109b7b3511411231a36425dd3aade65c68de1d;hp=9c9fa3ba9a31aaa196f3409617dd51895a1abafa;hpb=277b540c0764dd376dcf583acdc97a2b2fd3d8e6;p=bertos.git diff --git a/cpu.h b/cpu.h index 9c9fa3ba..1c8a62f3 100755 --- a/cpu.h +++ b/cpu.h @@ -17,6 +17,45 @@ /*#* *#* $Log$ + *#* Revision 1.28 2004/12/31 17:39:41 bernie + *#* Fix documentation. + *#* + *#* Revision 1.27 2004/12/31 17:02:47 bernie + *#* IRQ_SAVE_DISABLE(), IRQ_RESTORE(): Add null stubs for x86. + *#* + *#* Revision 1.26 2004/12/13 12:08:12 bernie + *#* DISABLE_IRQSAVE, ENABLE_IRQRESTORE, DISABLE_INTS, ENABLE_INTS: Remove obsolete macros. + *#* + *#* Revision 1.25 2004/12/08 08:31:02 bernie + *#* CPU_HARVARD: Define to 1 for AVR and DSP56K. + *#* + *#* Revision 1.24 2004/12/08 08:04:13 bernie + *#* Doxygen fixes. + *#* + *#* Revision 1.23 2004/11/16 22:41:58 bernie + *#* Support 64bit CPUs. + *#* + *#* Revision 1.22 2004/11/16 21:57:59 bernie + *#* CPU_IDLE: Rename from SCHEDULER_IDLE. + *#* + *#* Revision 1.21 2004/11/16 21:34:25 bernie + *#* Commonize obsolete names for IRQ macros; Doxygen fixes. + *#* + *#* Revision 1.20 2004/11/16 20:33:32 bernie + *#* CPU_HARVARD: New macro. + *#* + *#* Revision 1.19 2004/10/03 20:43:54 bernie + *#* Fix Doxygen markup. + *#* + *#* Revision 1.18 2004/10/03 18:36:31 bernie + *#* IRQ_GETSTATE(): New macro; Rename IRQ macros for consistency. + *#* + *#* Revision 1.17 2004/09/06 21:48:27 bernie + *#* ATOMIC(): New macro. + *#* + *#* Revision 1.16 2004/08/29 21:58:33 bernie + *#* Rename BITS_PER_XYZ macros; Add sanity checks. + *#* *#* Revision 1.15 2004/08/25 14:12:08 rasky *#* Aggiornato il comment block dei log RCS *#* @@ -39,22 +78,26 @@ #ifndef DEVLIB_CPU_H #define DEVLIB_CPU_H -#include "compiler.h" /* for uintXX_t, PP_CAT3(), PP_STRINGIZE() */ +#include "compiler.h" /* for uintXX_t */ -// Macros for determining CPU endianness +/*! + * \name Macros for determining CPU endianness. + * \{ + */ #define CPU_BIG_ENDIAN 0x1234 #define CPU_LITTLE_ENDIAN 0x3412 +/*\}*/ -// Macros to include cpu-specific version of the headers +/*! Macro to include cpu-specific versions of the headers. */ #define CPU_HEADER(module) PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).h) #if CPU_I196 - #define DISABLE_INTS disable_interrupt() - #define ENABLE_INTS enable_interrupt() #define NOP nop_instruction() + #define IRQ_DISABLE disable_interrupt() + #define IRQ_ENABLE enable_interrupt() typedef uint16_t cpuflags_t; // FIXME typedef unsigned int cpustack_t; @@ -64,12 +107,15 @@ #define CPU_STACK_GROWS_UPWARD 0 #define CPU_SP_ON_EMPTY_SLOT 0 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN + #define CPU_HARVARD 0 #elif CPU_X86 #define NOP asm volatile ("nop") - #define DISABLE_INTS /* nothing */ - #define ENABLE_INTS /* nothing */ + #define IRQ_DISABLE /* nothing */ + #define IRQ_ENABLE /* nothing */ + #define IRQ_SAVE_DISABLE(x) /* nothing */ + #define IRQ_RESTORE(x) /* nothing */ typedef uint32_t cpuflags_t; // FIXME typedef uint32_t cpustack_t; @@ -79,18 +125,20 @@ #define CPU_STACK_GROWS_UPWARD 0 #define CPU_SP_ON_EMPTY_SLOT 0 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN + #define CPU_HARVARD 0 #elif CPU_DSP56K #define NOP asm(nop) - #define DISABLE_INTS do { asm(bfset #0x0200,SR); asm(nop); } while (0) - #define ENABLE_INTS do { asm(bfclr #0x0200,SR); asm(nop); } while (0) + #define IRQ_DISABLE do { asm(bfset #0x0200,SR); asm(nop); } while (0) + #define IRQ_ENABLE do { asm(bfclr #0x0200,SR); asm(nop); } while (0) - #define DISABLE_IRQSAVE(x) \ + #define IRQ_SAVE_DISABLE(x) \ do { (void)x; asm(move SR,x); asm(bfset #0x0200,SR); } while (0) - #define ENABLE_IRQRESTORE(x) \ + #define IRQ_RESTORE(x) \ do { (void)x; asm(move x,SR); } while (0) + typedef uint16_t cpuflags_t; typedef unsigned int cpustack_t; @@ -100,21 +148,22 @@ #define CPU_STACK_GROWS_UPWARD 1 #define CPU_SP_ON_EMPTY_SLOT 0 #define CPU_BYTE_ORDER CPU_BIG_ENDIAN + #define CPU_HARVARD 1 /* Memory is word-addessed in the DSP56K */ - #define BITSP_PER_CHAR 16 - #define SIZEOF_SHORT 1 - #define SIZEOF_INT 1 - #define SIZEOF_LONG 2 - #define SIZEOF_PTR 1 + #define CPU_BITS_PER_CHAR 16 + #define SIZEOF_SHORT 1 + #define SIZEOF_INT 1 + #define SIZEOF_LONG 2 + #define SIZEOF_PTR 1 #elif CPU_AVR - #define NOP asm volatile ("nop" ::) - #define DISABLE_INTS asm volatile ("cli" ::) - #define ENABLE_INTS asm volatile ("sei" ::) + #define NOP asm volatile ("nop" ::) + #define IRQ_DISABLE asm volatile ("cli" ::) + #define IRQ_ENABLE asm volatile ("sei" ::) - #define DISABLE_IRQSAVE(x) \ + #define IRQ_SAVE_DISABLE(x) \ do { \ __asm__ __volatile__( \ "in %0,__SREG__\n\t" \ @@ -123,13 +172,23 @@ ); \ } while (0) - #define ENABLE_IRQRESTORE(x) \ + #define IRQ_RESTORE(x) \ do { \ __asm__ __volatile__( \ "out __SREG__,%0" : /* no outputs */ : "r" (x) : "cc" \ ); \ } while (0) + #define IRQ_GETSTATE() \ + ({ \ + uint8_t sreg; \ + __asm__ __volatile__( \ + "in %0,__SREG__\n\t" \ + : "=r" (sreg) /* no inputs & no clobbers */ \ + ); \ + (bool)(sreg & 0x80); \ + }) + typedef uint8_t cpuflags_t; typedef uint8_t cpustack_t; @@ -140,6 +199,7 @@ #define CPU_STACK_GROWS_UPWARD 0 #define CPU_SP_ON_EMPTY_SLOT 1 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN + #define CPU_HARVARD 1 /*! * Initialization value for registers in stack frame. @@ -151,6 +211,19 @@ #endif +/*! + * Execute \a CODE atomically with respect to interrupts. + * + * \see IRQ_SAVE_DISABLE IRQ_RESTORE + */ +#define ATOMIC(CODE) \ + do { \ + cpuflags_t __flags; \ + IRQ_SAVE_DISABLE(__flags); \ + CODE; \ + IRQ_RESTORE(__flags); \ + } while (0) + //! Default for macro not defined in the right arch section #ifndef CPU_REG_INIT_VALUE @@ -202,7 +275,8 @@ #if CPU_DSP56K - /* DSP56k pushes both PC and SR to the stack in the JSR instruction, but + /* + * DSP56k pushes both PC and SR to the stack in the JSR instruction, but * RTS discards SR while returning (it does not restore it). So we push * 0 to fake the same context. */ @@ -213,7 +287,8 @@ } while (0); #elif CPU_AVR - /* In AVR, the addresses are pushed into the stack as little-endian, while + /* + * In AVR, the addresses are pushed into the stack as little-endian, while * memory accesses are big-endian (actually, it's a 8-bit CPU, so there is * no natural endianess). */ @@ -231,23 +306,20 @@ /*! - * \def SIZEOF_CHAR SIZEOF_SHORT SIZEOF_INT SIZEOF_LONG SIZEOF_PTR - * \def BITS_PER_CHAR BITS_PER_SHORT BITS_PER_INT BITS_PER_LONG BITS_PER_PTR - * - * \brief Default type sizes + * \name Default type sizes. * * These defaults are reasonable for most 16/32bit machines. * Some of these macros may be overridden by CPU-specific code above. * - * ANSI C specifies that the following equations must be true: + * ANSI C requires that the following equations be true: * \code * sizeof(char) <= sizeof(short) <= sizeof(int) <= sizeof(long) * sizeof(float) <= sizeof(double) - * BITS_PER_CHAR >= 8 - * BITS_PER_SHORT >= 8 - * BITS_PER_INT >= 16 - * BITS_PER_LONG >= 32 - * \end code + * CPU_BITS_PER_CHAR >= 8 + * CPU_BITS_PER_SHORT >= 8 + * CPU_BITS_PER_INT >= 16 + * CPU_BITS_PER_LONG >= 32 + * \endcode * \{ */ #ifndef SIZEOF_CHAR @@ -267,37 +339,47 @@ #endif /* !SIZEOF_INT */ #ifndef SIZEOF_LONG -#define SIZEOF_LONG 4 +#if CPU_REG_BITS > 32 + #define SIZEOF_LONG 8 +#else + #define SIZEOF_LONG 4 +#endif #endif #ifndef SIZEOF_PTR #define SIZEOF_PTR SIZEOF_INT #endif -#ifndef BITS_PER_CHAR -#define BITS_PER_CHAR (SIZEOF_CHAR * 8) +#ifndef CPU_BITS_PER_CHAR +#define CPU_BITS_PER_CHAR (SIZEOF_CHAR * 8) #endif -#ifndef BITS_PER_SHORT -#define BITS_PER_SHORT (SIZEOF_SHORT * BITS_PER_CHAR) +#ifndef CPU_BITS_PER_SHORT +#define CPU_BITS_PER_SHORT (SIZEOF_SHORT * CPU_BITS_PER_CHAR) #endif -#ifndef BITS_PER_INT -#define BITS_PER_INT (SIZEOF_INT * BITS_PER_CHAR) +#ifndef CPU_BITS_PER_INT +#define CPU_BITS_PER_INT (SIZEOF_INT * CPU_BITS_PER_CHAR) #endif -#ifndef BITS_PER_LONG -#define BITS_PER_LONG (SIZEOF_LONG * BITS_PER_CHAR) +#ifndef CPU_BITS_PER_LONG +#define CPU_BITS_PER_LONG (SIZEOF_LONG * CPU_BITS_PER_CHAR) #endif -#ifndef BITS_PER_PTR -#define BITS_PER_PTR (SIZEOF_PTR * BITS_PER_CHAR) +#ifndef CPU_BITS_PER_PTR +#define CPU_BITS_PER_PTR (SIZEOF_PTR * CPU_BITS_PER_CHAR) #endif /*\}*/ +/* Sanity checks for the above definitions */ +STATIC_ASSERT(sizeof(char) == SIZEOF_CHAR); +STATIC_ASSERT(sizeof(short) == SIZEOF_SHORT); +STATIC_ASSERT(sizeof(long) == SIZEOF_LONG); +STATIC_ASSERT(sizeof(int) == SIZEOF_INT); + /*! - * \def SCHEDULER_IDLE + * \def CPU_IDLE * * \brief Invoked by the scheduler to stop the CPU when idle. * @@ -305,16 +387,19 @@ * profile system load with an external strobe, or to save CPU cycles * in hosted environments such as emulators. */ -#ifndef SCHEDULER_IDLE +#ifndef CPU_IDLE #if defined(ARCH_EMUL) && (ARCH & ARCH_EMUL) /* This emulator hook should yield the CPU to the host. */ EXTERN_C_BEGIN void SchedulerIdle(void); EXTERN_C_END - #define SCHEDULER_IDLE SchedulerIdle() + #define CPU_IDLE SchedulerIdle() #else /* !ARCH_EMUL */ - #define SCHEDULER_IDLE do { /* nothing */ } while (0) + #define CPU_IDLE do { /* nothing */ } while (0) #endif /* !ARCH_EMUL */ -#endif /* !SCHEDULER_IDLE */ +#endif /* !CPU_IDLE */ + +/* OBSOLETE */ +#define SCHEDULER_IDLE CPU_IDLE #endif /* DEVLIB_CPU_H */