X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=cpu.h;h=33106f30c8c340179a91802792d793a2fc85c4ed;hb=43268c92c3e0cd4fe8997aabcfc908715f258631;hp=fb249c223edad3726bcd4047af791b87cf7c83e8;hpb=ef541df3aeda1fe5969b1285c2b4d73d65e8375f;p=bertos.git

diff --git a/cpu.h b/cpu.h
index fb249c22..33106f30 100755
--- a/cpu.h
+++ b/cpu.h
@@ -17,6 +17,21 @@
 
 /*#*
  *#* $Log$
+ *#* Revision 1.24  2004/12/08 08:04:13  bernie
+ *#* Doxygen fixes.
+ *#*
+ *#* Revision 1.23  2004/11/16 22:41:58  bernie
+ *#* Support 64bit CPUs.
+ *#*
+ *#* Revision 1.22  2004/11/16 21:57:59  bernie
+ *#* CPU_IDLE: Rename from SCHEDULER_IDLE.
+ *#*
+ *#* Revision 1.21  2004/11/16 21:34:25  bernie
+ *#* Commonize obsolete names for IRQ macros; Doxygen fixes.
+ *#*
+ *#* Revision 1.20  2004/11/16 20:33:32  bernie
+ *#* CPU_HARVARD: New macro.
+ *#*
  *#* Revision 1.19  2004/10/03 20:43:54  bernie
  *#* Fix Doxygen markup.
  *#*
@@ -54,19 +69,23 @@
 #include "compiler.h" /* for uintXX_t, PP_CAT3(), PP_STRINGIZE() */
 
 
-// Macros for determining CPU endianness
+/*!
+ * \name Macros for determining CPU endianness.
+ * \{
+ */
 #define CPU_BIG_ENDIAN    0x1234
 #define CPU_LITTLE_ENDIAN 0x3412
+/*\}*/
 
-// Macros to include cpu-specific version of the headers
+/*! Macro to include cpu-specific versions of the headers. */
 #define CPU_HEADER(module)          PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).h)
 
 
 #if CPU_I196
 
-	#define DISABLE_INTS            disable_interrupt()
-	#define ENABLE_INTS             enable_interrupt()
 	#define NOP                     nop_instruction()
+	#define IRQ_DISABLE             disable_interrupt()
+	#define IRQ_ENABLE              enable_interrupt()
 
 	typedef uint16_t cpuflags_t; // FIXME
 	typedef unsigned int cpustack_t;
@@ -76,12 +95,13 @@
 	#define CPU_STACK_GROWS_UPWARD  0
 	#define CPU_SP_ON_EMPTY_SLOT	0
 	#define CPU_BYTE_ORDER          CPU_LITTLE_ENDIAN
+	#define CPU_HARVARD		0
 
 #elif CPU_X86
 
 	#define NOP                     asm volatile ("nop")
-	#define DISABLE_INTS            /* nothing */
-	#define ENABLE_INTS             /* nothing */
+	#define IRQ_DISABLE             /* nothing */
+	#define IRQ_ENABLE              /* nothing */
 
 	typedef uint32_t cpuflags_t; // FIXME
 	typedef uint32_t cpustack_t;
@@ -91,18 +111,20 @@
 	#define CPU_STACK_GROWS_UPWARD  0
 	#define CPU_SP_ON_EMPTY_SLOT	0
 	#define CPU_BYTE_ORDER          CPU_LITTLE_ENDIAN
+	#define CPU_HARVARD		0
 
 #elif CPU_DSP56K
 
 	#define NOP                     asm(nop)
-	#define DISABLE_INTS            do { asm(bfset #0x0200,SR); asm(nop); } while (0)
-	#define ENABLE_INTS             do { asm(bfclr #0x0200,SR); asm(nop); } while (0)
+	#define IRQ_DISABLE             do { asm(bfset #0x0200,SR); asm(nop); } while (0)
+	#define IRQ_ENABLE              do { asm(bfclr #0x0200,SR); asm(nop); } while (0)
 
-	#define DISABLE_IRQSAVE(x)  \
+	#define IRQ_SAVE_DISABLE(x)  \
 		do { (void)x; asm(move SR,x); asm(bfset #0x0200,SR); } while (0)
-	#define ENABLE_IRQRESTORE(x)  \
+	#define IRQ_RESTORE(x)  \
 		do { (void)x; asm(move x,SR); } while (0)
 
+
 	typedef uint16_t cpuflags_t;
 	typedef unsigned int cpustack_t;
 
@@ -152,12 +174,6 @@
 		(bool)(sreg & 0x80); \
 	})
 
-	/* OBSOLETE NAMES */
-	#define DISABLE_INTS IRQ_DISABLE
-	#define ENABLE_INTS  IRQ_ENABLE
-	#define DISABLE_IRQSAVE(x)   IRQ_SAVE_DISABLE(x)
-	#define ENABLE_IRQRESTORE(x) IRQ_RESTORE(x)
-
 	typedef uint8_t cpuflags_t;
 	typedef uint8_t cpustack_t;
 
@@ -179,6 +195,12 @@
 
 #endif
 
+/* OBSOLETE NAMES */
+#define DISABLE_INTS         IRQ_DISABLE
+#define ENABLE_INTS          IRQ_ENABLE
+#define DISABLE_IRQSAVE(x)   IRQ_SAVE_DISABLE(x)
+#define ENABLE_IRQRESTORE(x) IRQ_RESTORE(x)
+
 /*!
  * Execute \a CODE atomically with respect to interrupts.
  *
@@ -243,7 +265,8 @@
 
 
 #if CPU_DSP56K
-	/* DSP56k pushes both PC and SR to the stack in the JSR instruction, but
+	/*
+	 * DSP56k pushes both PC and SR to the stack in the JSR instruction, but
 	 * RTS discards SR while returning (it does not restore it). So we push
 	 * 0 to fake the same context.
 	 */
@@ -254,7 +277,8 @@
 		} while (0);
 
 #elif CPU_AVR
-	/* In AVR, the addresses are pushed into the stack as little-endian, while
+	/*
+	 * In AVR, the addresses are pushed into the stack as little-endian, while
 	 * memory accesses are big-endian (actually, it's a 8-bit CPU, so there is
 	 * no natural endianess).
 	 */
@@ -272,11 +296,7 @@
 
 
 /*!
- * \name Default type sizes
- *
- * \def SIZEOF_CHAR SIZEOF_SHORT SIZEOF_INT SIZEOF_LONG SIZEOF_PTR
- * \def CPU_BITS_PER_CHAR CPU_BITS_PER_SHORT CPU_BITS_PER_INT
- * \def CPU_BITS_PER_LONG CPU_BITS_PER_PTR
+ * \name Default type sizes.
  *
  * These defaults are reasonable for most 16/32bit machines.
  * Some of these macros may be overridden by CPU-specific code above.
@@ -309,7 +329,11 @@
 #endif /* !SIZEOF_INT */
 
 #ifndef SIZEOF_LONG
-#define SIZEOF_LONG  4
+#if CPU_REG_BITS > 32
+	#define SIZEOF_LONG  8
+#else
+	#define SIZEOF_LONG  4
+#endif
 #endif
 
 #ifndef SIZEOF_PTR
@@ -353,16 +377,19 @@ STATIC_ASSERT(sizeof(int) == SIZEOF_INT);
  * profile system load with an external strobe, or to save CPU cycles
  * in hosted environments such as emulators.
  */
-#ifndef SCHEDULER_IDLE
+#ifndef CPU_IDLE
 	#if defined(ARCH_EMUL) && (ARCH & ARCH_EMUL)
 		/* This emulator hook should yield the CPU to the host.  */
 		EXTERN_C_BEGIN
 		void SchedulerIdle(void);
 		EXTERN_C_END
-		#define SCHEDULER_IDLE SchedulerIdle()
+		#define CPU_IDLE SchedulerIdle()
 	#else /* !ARCH_EMUL */
-		#define SCHEDULER_IDLE do { /* nothing */ } while (0)
+		#define CPU_IDLE do { /* nothing */ } while (0)
 	#endif /* !ARCH_EMUL */
-#endif /* !SCHEDULER_IDLE */
+#endif /* !CPU_IDLE */
+
+/* OBSOLETE */
+#define SCHEDULER_IDLE CPU_IDLE
 
 #endif /* DEVLIB_CPU_H */