X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=cpu.h;h=c8a242f22645931af2252572d9ed3d8027a21d46;hb=d8c41d44af59c3b699736024da1ccc11efa52384;hp=626bd3e03b7dcf91dabe14d186672ce0b95c8694;hpb=b81657391042e045769c544cf749f2f382d6e9a5;p=bertos.git

diff --git a/cpu.h b/cpu.h
index 626bd3e0..c8a242f2 100755
--- a/cpu.h
+++ b/cpu.h
@@ -3,7 +3,7 @@
  * <!--
  * Copyright 2004 Develer S.r.l. (http://www.develer.com/)
  * Copyright 2004 Giovanni Bajo
- * All Rights Reserved.
+ * This file is part of DevLib - See devlib/README for information.
  * -->
  *
  * \brief CPU-specific definitions
@@ -11,10 +11,33 @@
  * \version $Id$
  *
  * \author Giovanni Bajo <rasky@develer.com>
+ * \author Bernardo Innocenti <bernie@develer.com>
+ * \author Stefano Fedrigo <aleph@develer.com>
  */
 
 /*
  * $Log$
+ * Revision 1.8  2004/07/30 14:15:53  rasky
+ * Nuovo supporto unificato per detect della CPU
+ *
+ * Revision 1.7  2004/07/20 23:26:48  bernie
+ * Fix two errors introduced by previous commit.
+ *
+ * Revision 1.6  2004/07/20 23:12:16  bernie
+ * Rationalize and document SCHEDULER_IDLE.
+ *
+ * Revision 1.5  2004/07/20 16:20:35  bernie
+ * Move byte-order macros to mware/byteorder.h; Add missing author names.
+ *
+ * Revision 1.4  2004/07/20 16:06:04  bernie
+ * Add macros to handle endianess issues.
+ *
+ * Revision 1.3  2004/07/18 21:49:51  bernie
+ * Fixes for GCC 3.5.
+ *
+ * Revision 1.2  2004/06/03 11:27:09  bernie
+ * Add dual-license information.
+ *
  * Revision 1.1  2004/05/23 17:48:35  bernie
  * Add top-level files.
  *
@@ -24,15 +47,23 @@
 
 #include "compiler.h"
 
+
 //! Initialization value for registers in stack frame
 #define CPU_REG_INIT_VALUE(reg)     0
 
-#if defined(__IAR_SYSTEMS_ICC) || defined(__IAR_SYSTEMS_ICC__)  /* 80C196 */
+// Macros for determining CPU endianess
+#define CPU_BIG_ENDIAN    0x1234
+#define CPU_LITTLE_ENDIAN 0x3412
+
+// Macros to include cpu-specific version of the headers
+#define CPU_HEADER(module)          PP_STRINGIZE(PP_CAT4(module, _, CPU_ID, .h))
+
+
+#if CPU_I196
 
 	#define DISABLE_INTS            disable_interrupt()
 	#define ENABLE_INTS             enable_interrupt()
 	#define NOP                     nop_instruction()
-	#define SCHEDULER_IDLE          /* Hmmm... could we go in STOP mode? */
 
 	typedef uint16_t cpuflags_t; // FIXME
 	typedef unsigned int cpustack_t;
@@ -40,13 +71,13 @@
 	#define CPU_REGS_CNT            16
 	#define CPU_STACK_GROWS_UPWARD  0
 	#define CPU_SP_ON_EMPTY_SLOT	0
+	#define CPU_BYTE_ORDER          CPU_LITTLE_ENDIAN
 
-#elif defined(__i386__) || defined(_MSC_VER) /* x86 */
+#elif CPU_X86
 
 	#define NOP                     asm volatile ("nop")
 	#define DISABLE_INTS            /* nothing */
 	#define ENABLE_INTS             /* nothing */
-	#define SCHEDULER_IDLE          SchedulerIdle()
 
 	typedef uint32_t cpuflags_t; // FIXME
 	typedef uint32_t cpustack_t;
@@ -54,13 +85,13 @@
 	#define CPU_REGS_CNT            7
 	#define CPU_STACK_GROWS_UPWARD  0
 	#define CPU_SP_ON_EMPTY_SLOT	0
+	#define CPU_BYTE_ORDER          CPU_LITTLE_ENDIAN
 
-#elif defined(__m56800E__) || defined(__m56800__) /* DSP56K */
+#elif CPU_DSP56K
 
 	#define NOP                     asm(nop)
 	#define DISABLE_INTS            do { asm(bfset #0x0200,SR); asm(nop); } while (0)
 	#define ENABLE_INTS             do { asm(bfclr #0x0200,SR); asm(nop); } while (0)
-	#define SCHEDULER_IDLE          /* nothing */
 
 	#define DISABLE_IRQSAVE(x)  \
 		do { asm(move SR,x); asm(bfset #0x0200,SR); } while (0)
@@ -74,6 +105,7 @@
 	#define CPU_SAVED_REGS_CNT      28
 	#define CPU_STACK_GROWS_UPWARD  1
 	#define CPU_SP_ON_EMPTY_SLOT	0
+	#define CPU_BYTE_ORDER          CPU_BIG_ENDIAN
 
 	#undef CPU_REG_INIT_VALUE
 	INLINE uint16_t CPU_REG_INIT_VALUE(int reg)
@@ -91,10 +123,9 @@
 
 #elif defined (__AVR__)
 
-	#define NOP                     asm volatile ("nop")
-	#define DISABLE_INTS            cli()
-	#define ENABLE_INTS             sei()
-	#define SCHEDULER_IDLE          /* nothing */
+	#define NOP                     asm volatile ("nop" ::)
+	#define DISABLE_INTS            asm volatile ("cli" ::)
+	#define ENABLE_INTS             asm volatile ("sei" ::)
 
 	#define DISABLE_IRQSAVE(x) \
 	do { \
@@ -119,9 +150,7 @@
 	#define CPU_SAVED_REGS_CNT      18
 	#define CPU_STACK_GROWS_UPWARD  0
 	#define CPU_SP_ON_EMPTY_SLOT	1
-
-#else
-	#error Unknown CPU
+	#define CPU_BYTE_ORDER          CPU_LITTLE_ENDIAN
 #endif
 
 
@@ -168,7 +197,7 @@
 #endif
 
 
-#if defined(__m56800E__) || defined(__m56800__)
+#if CPU_DSP56K
 	/* DSP56k pushes both PC and SR to the stack in the JSR instruction, but
 	 * RTS discards SR while returning (it does not restore it). So we push
 	 * 0 to fake the same context.
@@ -196,4 +225,25 @@
 		CPU_PUSH_WORD((sp), (func))
 #endif
 
+
+/*!
+ * \name SCHEDULER_IDLE
+ *
+ * \brief Invoked by the scheduler to stop the CPU when idle.
+ *
+ * This hook can be redefined to put the CPU in low-power mode, or to
+ * profile system load with an external strobe, or to save CPU cycles
+ * in hosted environments such as emulators.
+ */
+#ifndef SCHEDULER_IDLE
+	#if defined(ARCH_EMUL) && (ARCH & ARCH_EMUL)
+		/* This emulator hook should yeld the CPU to the host.  */
+		EXTERN_C_BEGIN
+		void SchedulerIdle(void);
+		EXTERN_C_END
+	#else /* !ARCH_EMUL */
+		#define SCHEDULER_IDLE /* nothing */
+	#endif /* !ARCH_EMUL */
+#endif /* !SCHEDULER_IDLE */
+
 #endif /* CPU_H */