X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=cpu.h;h=ef3e15166930b1e9e6ac66a10625ddfa29fb14ed;hb=4560fc1a4dc7c27243d7f8afa9a1291e646c2f8b;hp=8d9ed1db923d00955f9aa9fc57bc1cfd26d2d57c;hpb=20e373712db1c78967b0491593fa139fc3ea0aad;p=bertos.git

diff --git a/cpu.h b/cpu.h
index 8d9ed1db..ef3e1516 100755
--- a/cpu.h
+++ b/cpu.h
@@ -17,6 +17,25 @@
 
 /*
  * $Log$
+ * Revision 1.12  2004/08/14 19:37:57  rasky
+ * Merge da SC: macros.h, pool.h, BIT_CHANGE, nome dei processi, etc.
+ *
+ * Revision 1.11  2004/08/05 17:39:56  bernie
+ * Fix a Doxygen tag.
+ *
+ * Revision 1.10  2004/08/02 20:20:29  aleph
+ * Merge from project_ks
+ *
+ * Revision 1.9  2004/07/30 14:24:16  rasky
+ * Task switching con salvataggio perfetto stato di interrupt (SR)
+ * Kernel monitor per dump informazioni su stack dei processi
+ *
+ * Revision 1.8  2004/07/30 14:15:53  rasky
+ * Nuovo supporto unificato per detect della CPU
+ *
+ * Revision 1.7  2004/07/20 23:26:48  bernie
+ * Fix two errors introduced by previous commit.
+ *
  * Revision 1.6  2004/07/20 23:12:16  bernie
  * Rationalize and document SCHEDULER_IDLE.
  *
@@ -41,15 +60,16 @@
 
 #include "compiler.h"
 
-//! Initialization value for registers in stack frame
-#define CPU_REG_INIT_VALUE(reg)     0
 
 // Macros for determining CPU endianness
 #define CPU_BIG_ENDIAN    0x1234
 #define CPU_LITTLE_ENDIAN 0x3412
 
+// Macros to include cpu-specific version of the headers
+#define CPU_HEADER(module)          PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).h)
+
 
-#if defined(__IAR_SYSTEMS_ICC) || defined(__IAR_SYSTEMS_ICC__)  /* 80C196 */
+#if CPU_I196
 
 	#define DISABLE_INTS            disable_interrupt()
 	#define ENABLE_INTS             enable_interrupt()
@@ -63,7 +83,7 @@
 	#define CPU_SP_ON_EMPTY_SLOT	0
 	#define CPU_BYTE_ORDER          CPU_LITTLE_ENDIAN
 
-#elif defined(__i386__) || defined(_MSC_VER) /* x86 */
+#elif CPU_X86
 
 	#define NOP                     asm volatile ("nop")
 	#define DISABLE_INTS            /* nothing */
@@ -77,41 +97,27 @@
 	#define CPU_SP_ON_EMPTY_SLOT	0
 	#define CPU_BYTE_ORDER          CPU_LITTLE_ENDIAN
 
-#elif defined(__m56800E__) || defined(__m56800__) /* DSP56K */
+#elif CPU_DSP56K
 
 	#define NOP                     asm(nop)
 	#define DISABLE_INTS            do { asm(bfset #0x0200,SR); asm(nop); } while (0)
 	#define ENABLE_INTS             do { asm(bfclr #0x0200,SR); asm(nop); } while (0)
 
 	#define DISABLE_IRQSAVE(x)  \
-		do { asm(move SR,x); asm(bfset #0x0200,SR); } while (0)
+		do { (void)x; asm(move SR,x); asm(bfset #0x0200,SR); } while (0)
 	#define ENABLE_IRQRESTORE(x)  \
-		do { asm(move x,SR); } while (0)
+		do { (void)x; asm(move x,SR); } while (0)
 
 	typedef uint16_t cpuflags_t;
 	typedef unsigned int cpustack_t;
 
 	#define CPU_REGS_CNT            FIXME
-	#define CPU_SAVED_REGS_CNT      28
+	#define CPU_SAVED_REGS_CNT      8
 	#define CPU_STACK_GROWS_UPWARD  1
 	#define CPU_SP_ON_EMPTY_SLOT	0
 	#define CPU_BYTE_ORDER          CPU_BIG_ENDIAN
 
-	#undef CPU_REG_INIT_VALUE
-	INLINE uint16_t CPU_REG_INIT_VALUE(int reg)
-	{
-		if (reg == 14)
-		{
-			uint16_t omr_img;
-			asm(move OMR, omr_img);
-			return omr_img & (BV(3)/*EX*/ | BV(1)/*MB*/ | BV(0)/*MA*/);
-		}
-		else if (reg == 16)/*M01*/
-			return 0xFFFF;
-		return 0;
-	}
-
-#elif defined (__AVR__)
+#elif CPU_AVR
 
 	#define NOP                     asm volatile ("nop" ::)
 	#define DISABLE_INTS            asm volatile ("cli" ::)
@@ -136,13 +142,27 @@
 	typedef uint8_t cpuflags_t;
 	typedef uint8_t cpustack_t;
 
-	#define CPU_REGS_CNT            32
-	#define CPU_SAVED_REGS_CNT      18
+	/* Register counts include SREG too */
+	#define CPU_REGS_CNT            33
+	#define CPU_SAVED_REGS_CNT      19
 	#define CPU_STACK_GROWS_UPWARD  0
 	#define CPU_SP_ON_EMPTY_SLOT	1
 	#define CPU_BYTE_ORDER          CPU_LITTLE_ENDIAN
-#else
-	#error Unknown CPU
+
+	/*!
+	 * Initialization value for registers in stack frame.
+	 * The register index is not directly corrispondent to CPU
+	 * register numbers. Index 0 is the SREG register: the initial
+	 * value is all 0 but the interrupt bit (bit 7).
+	 */
+	#define CPU_REG_INIT_VALUE(reg) (reg == 0 ? 0x80 : 0)
+
+#endif
+
+
+//! Default for macro not defined in the right arch section
+#ifndef CPU_REG_INIT_VALUE
+	#define CPU_REG_INIT_VALUE(reg)     0
 #endif
 
 
@@ -189,7 +209,7 @@
 #endif
 
 
-#if defined(__m56800E__) || defined(__m56800__)
+#if CPU_DSP56K
 	/* DSP56k pushes both PC and SR to the stack in the JSR instruction, but
 	 * RTS discards SR while returning (it does not restore it). So we push
 	 * 0 to fake the same context.
@@ -197,10 +217,10 @@
 	#define CPU_PUSH_CALL_CONTEXT(sp, func) \
 		do { \
 			CPU_PUSH_WORD((sp), (func)); \
-			CPU_PUSH_WORD((sp), 0); \
+			CPU_PUSH_WORD((sp), 0x100); \
 		} while (0);
 
-#elif defined (__AVR__)
+#elif CPU_AVR
 	/* In AVR, the addresses are pushed into the stack as little-endian, while
 	 * memory accesses are big-endian (actually, it's a 8-bit CPU, so there is
 	 * no natural endianess).
@@ -219,7 +239,7 @@
 
 
 /*!
- * \name SCHEDULER_IDLE
+ * \def SCHEDULER_IDLE
  *
  * \brief Invoked by the scheduler to stop the CPU when idle.
  *
@@ -228,8 +248,8 @@
  * in hosted environments such as emulators.
  */
 #ifndef SCHEDULER_IDLE
-	#if (ARCH & ARCH_EMUL)
-		/* This emulator hook should yeld the CPU to the host.  */
+	#if defined(ARCH_EMUL) && (ARCH & ARCH_EMUL)
+		/* This emulator hook should yield the CPU to the host.  */
 		EXTERN_C_BEGIN
 		void SchedulerIdle(void);
 		EXTERN_C_END