X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=cpu.h;h=fb249c223edad3726bcd4047af791b87cf7c83e8;hb=7be79ed82e47606fa35a4ef58f11c4723d22087a;hp=4b762449c9adc67a295d5fcb8aef9b03f0aff382;hpb=6cbc8596a105e183d9f805a6deb4fae224e9baac;p=bertos.git

diff --git a/cpu.h b/cpu.h
index 4b762449..fb249c22 100755
--- a/cpu.h
+++ b/cpu.h
@@ -17,6 +17,15 @@
 
 /*#*
  *#* $Log$
+ *#* Revision 1.19  2004/10/03 20:43:54  bernie
+ *#* Fix Doxygen markup.
+ *#*
+ *#* Revision 1.18  2004/10/03 18:36:31  bernie
+ *#* IRQ_GETSTATE(): New macro; Rename IRQ macros for consistency.
+ *#*
+ *#* Revision 1.17  2004/09/06 21:48:27  bernie
+ *#* ATOMIC(): New macro.
+ *#*
  *#* Revision 1.16  2004/08/29 21:58:33  bernie
  *#* Rename BITS_PER_XYZ macros; Add sanity checks.
  *#*
@@ -113,11 +122,11 @@
 
 #elif CPU_AVR
 
-	#define NOP                     asm volatile ("nop" ::)
-	#define DISABLE_INTS            asm volatile ("cli" ::)
-	#define ENABLE_INTS             asm volatile ("sei" ::)
+	#define NOP           asm volatile ("nop" ::)
+	#define IRQ_DISABLE   asm volatile ("cli" ::)
+	#define IRQ_ENABLE    asm volatile ("sei" ::)
 
-	#define DISABLE_IRQSAVE(x) \
+	#define IRQ_SAVE_DISABLE(x) \
 	do { \
 		__asm__ __volatile__( \
 			"in %0,__SREG__\n\t" \
@@ -126,13 +135,29 @@
 		); \
 	} while (0)
 
-	#define ENABLE_IRQRESTORE(x) \
+	#define IRQ_RESTORE(x) \
 	do { \
 		__asm__ __volatile__( \
 			"out __SREG__,%0" : /* no outputs */ : "r" (x) : "cc" \
 		); \
 	} while (0)
 
+	#define IRQ_GETSTATE() \
+	({ \
+		uint8_t sreg; \
+		__asm__ __volatile__( \
+			"in %0,__SREG__\n\t" \
+			: "=r" (sreg)  /* no inputs & no clobbers */ \
+		); \
+		(bool)(sreg & 0x80); \
+	})
+
+	/* OBSOLETE NAMES */
+	#define DISABLE_INTS IRQ_DISABLE
+	#define ENABLE_INTS  IRQ_ENABLE
+	#define DISABLE_IRQSAVE(x)   IRQ_SAVE_DISABLE(x)
+	#define ENABLE_IRQRESTORE(x) IRQ_RESTORE(x)
+
 	typedef uint8_t cpuflags_t;
 	typedef uint8_t cpustack_t;
 
@@ -154,6 +179,19 @@
 
 #endif
 
+/*!
+ * Execute \a CODE atomically with respect to interrupts.
+ *
+ * \see ENABLE_IRQSAVE DISABLE_IRQRESTORE
+ */
+#define ATOMIC(CODE) \
+	do { \
+		cpuflags_t __flags; \
+		DISABLE_IRQSAVE(__flags); \
+		CODE; \
+		ENABLE_IRQRESTORE(__flags); \
+	} while (0)
+
 
 //! Default for macro not defined in the right arch section
 #ifndef CPU_REG_INIT_VALUE
@@ -251,7 +289,7 @@
  *   CPU_BITS_PER_SHORT >= 8
  *   CPU_BITS_PER_INT   >= 16
  *   CPU_BITS_PER_LONG  >= 32
- * \end code
+ * \endcode
  * \{
  */
 #ifndef SIZEOF_CHAR