X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=drv%2Feeprom.c;h=b7238335cf0c01fd3c76f044bd7cbc26cd9fcf64;hb=32841198fc4373115f71761a05088d10f0826223;hp=0f301effa709c41d463398d9f45d5033ed69e849;hpb=8ff088ff4cf0ddbff09c6630e36370bf25f33535;p=bertos.git diff --git a/drv/eeprom.c b/drv/eeprom.c index 0f301eff..b7238335 100755 --- a/drv/eeprom.c +++ b/drv/eeprom.c @@ -2,7 +2,7 @@ * \file * * * \brief Driver for the 24xx16 and 24xx256 I2C EEPROMS (implementation) @@ -16,6 +16,18 @@ /*#* *#* $Log$ + *#* Revision 1.15 2005/01/06 16:09:40 aleph + *#* Split twi/eeprom functions from eeprom module in separate twi module + *#* + *#* Revision 1.14 2004/12/13 12:07:06 bernie + *#* DISABLE_IRQSAVE/ENABLE_IRQRESTORE: Convert to IRQ_SAVE_DISABLE/IRQ_RESTORE. + *#* + *#* Revision 1.13 2004/11/16 20:58:51 bernie + *#* Add write verify. + *#* + *#* Revision 1.12 2004/11/02 17:50:01 bernie + *#* CONFIG_EEPROM_VERIFY: New config option. + *#* *#* Revision 1.11 2004/10/26 08:35:31 bernie *#* Reset watchdog for long operations. *#* @@ -53,188 +65,27 @@ #include "eeprom.h" -#include -#include /* cpu_to_be16() */ #include -#include +#include // CONFIG_EEPROM_VERIFY #include // MIN() +#include +#include +#include // cpu_to_be16() -#include // memset() - -#include - - -/* Wait for TWINT flag set: bus is ready */ -#define WAIT_TWI_READY do {} while (!(TWCR & BV(TWINT))) - -/*! \name EEPROM control codes */ -/*@{*/ -#define SLA_W 0xA0 -#define SLA_R 0xA1 -/*@}*/ - - -/*! - * Send START condition on the bus. - * - * \return true on success, false otherwise. - */ -static bool twi_start(void) -{ - TWCR = BV(TWINT) | BV(TWSTA) | BV(TWEN); - WAIT_TWI_READY; - - if (TW_STATUS == TW_START || TW_STATUS == TW_REP_START) - return true; - - DB(kprintf("!TW_(REP)START: %x\n", TWSR);) - return false; -} - - -/*! - * Send START condition and select slave for write. - * - * \return true on success, false otherwise. - */ -static bool twi_start_w(uint8_t slave_addr) -{ - ASSERT(slave_addr < 8); - - /* - * Loop on the select write sequence: when the eeprom is busy - * writing previously sent data it will reply to the SLA_W - * control byte with a NACK. In this case, we must - * keep trying until the eeprom responds with an ACK. - */ - while (twi_start()) - { - TWDR = SLA_W | (slave_addr << 1); - TWCR = BV(TWINT) | BV(TWEN); - WAIT_TWI_READY; - - if (TW_STATUS == TW_MT_SLA_ACK) - return true; - else if (TW_STATUS != TW_MT_SLA_NACK) - { - DB(kprintf("!TW_MT_SLA_(N)ACK: %x\n", TWSR);) - break; - } - } - - return false; -} - - -/*! - * Send START condition and select slave for read. - * - * \return true on success, false otherwise. - */ -static bool twi_start_r(uint8_t slave_addr) -{ - ASSERT(slave_addr < 8); - - if (twi_start()) - { - TWDR = SLA_R | (slave_addr << 1); - TWCR = BV(TWINT) | BV(TWEN); - WAIT_TWI_READY; - - if (TW_STATUS == TW_MR_SLA_ACK) - return true; - - DB(kprintf("!TW_MR_SLA_ACK: %x\n", TWSR);) - } - - return false; -} - - -/*! - * Send STOP condition. - */ -static void twi_stop(void) -{ - TWCR = BV(TWINT) | BV(TWEN) | BV(TWSTO); -} - - -/*! - * Send a sequence of bytes in master transmitter mode - * to the selected slave device through the TWI bus. - * - * \return true on success, false on error. - */ -static bool twi_send(const void *_buf, size_t count) -{ - const uint8_t *buf = (const uint8_t *)_buf; - - while (count--) - { - TWDR = *buf++; - TWCR = BV(TWINT) | BV(TWEN); - WAIT_TWI_READY; - if (TW_STATUS != TW_MT_DATA_ACK) - { - DB(kprintf("!TW_MT_DATA_ACK: %x\n", TWSR);) - return false; - } - } - - return true; -} - - -/*! - * Receive a sequence of one or more bytes from the - * selected slave device in master receive mode through - * the TWI bus. - * - * Received data is placed in \c buf. - * - * \return true on success, false on error - */ -static bool twi_recv(void *_buf, size_t count) -{ - uint8_t *buf = (uint8_t *)_buf; +#include // memset() - /* - * When reading the last byte the TWEA bit is not - * set, and the eeprom should answer with NACK - */ - while (count--) - { - TWCR = BV(TWINT) | BV(TWEN) | (count ? BV(TWEA) : 0); - WAIT_TWI_READY; - if (count) - { - if (TW_STATUS != TW_MR_DATA_ACK) - { - DB(kprintf("!TW_MR_DATA_ACK: %x\n", TWSR);) - return false; - } - } - else - { - if (TW_STATUS != TW_MR_DATA_NACK) - { - DB(kprintf("!TW_MR_DATA_NACK: %x\n", TWSR);) - return false; - } - } - *buf++ = TWDR; - } +// Configuration sanity checks +#if !defined(CONFIG_EEPROM_VERIFY) || (CONFIG_EEPROM_VERIFY != 0 && CONFIG_EEPROM_VERIFY != 1) + #error CONFIG_EEPROM_VERIFY must be defined to either 0 or 1 +#endif - return true; -} /*! * Copy \c count bytes from buffer \c buf to * eeprom at address \c addr. */ -bool eeprom_write(e2addr_t addr, const void *buf, size_t count) +static bool eeprom_writeRaw(e2addr_t addr, const void *buf, size_t count) { bool result = true; ASSERT(addr + count <= EEPROM_SIZE); @@ -289,8 +140,71 @@ bool eeprom_write(e2addr_t addr, const void *buf, size_t count) buf = ((const char *)buf) + size; } + if (!result) + TRACEMSG("Write error!"); + return result; +} + + +#if CONFIG_EEPROM_VERIFY +/*! + * Check that the contents of an EEPROM range + * match with a provided data buffer. + * + * \return true on success. + */ +static bool eeprom_verify(e2addr_t addr, const void *buf, size_t count) +{ + uint8_t verify_buf[16]; + bool result = true; + + while (count && result) + { + /* Split read in smaller pieces */ + size_t size = MIN(count, sizeof verify_buf); + + /* Read back buffer */ + if (eeprom_read(addr, verify_buf, size)) + { + if (memcmp(buf, verify_buf, size) != 0) + { + TRACEMSG("Data mismatch!"); + result = false; + } + } + else + { + TRACEMSG("Read error!"); + result = false; + } + + /* Update count and addr for next operation */ + count -= size; + addr += size; + buf = ((const char *)buf) + size; + } + return result; } +#endif /* CONFIG_EEPROM_VERIFY */ + + +bool eeprom_write(e2addr_t addr, const void *buf, size_t count) +{ +#if CONFIG_EEPROM_VERIFY + int retries = 5; + + while (retries--) + if (eeprom_writeRaw(addr, buf, count) + && eeprom_verify(addr, buf, count)) + return true; + + return false; + +#else /* !CONFIG_EEPROM_VERIFY */ + return eeprom_writeRaw(addr, buf, count); +#endif /* !CONFIG_EEPROM_VERIFY */ +} /*! @@ -333,6 +247,8 @@ bool eeprom_read(e2addr_t addr, void *buf, size_t count) twi_stop(); + if (!res) + TRACEMSG("Read error!"); return res; } @@ -392,31 +308,7 @@ void eeprom_erase(e2addr_t addr, size_t count) */ void eeprom_init(void) { - cpuflags_t flags; - DISABLE_IRQSAVE(flags); - -#if defined(__AVR_ATmega64__) - PORTD |= BV(PD0) | BV(PD1); - DDRD |= BV(PD0) | BV(PD1); -#elif defined(__AVR_ATmega8__) - PORTC |= BV(PC4) | BV(PC5); - DDRC |= BV(PC4) | BV(PC5); -#else - #error Unsupported architecture -#endif - - /* - * Set speed: - * F = CLOCK_FREQ / (16 + 2*TWBR * 4^TWPS) - */ - #define TWI_FREQ 300000 /* 300 kHz */ - #define TWI_PRESC 1 /* 4 ^ TWPS */ - - TWBR = (CLOCK_FREQ / (2 * TWI_FREQ * TWI_PRESC)) - (8 / TWI_PRESC); - TWSR = 0; - TWCR = BV(TWEN); - - ENABLE_IRQRESTORE(flags); + twi_init(); } @@ -432,11 +324,15 @@ void eeprom_test(void) // Write something to EEPROM using unaligned sequential writes for (i = 0; i < 42; ++i) + { + wdt_reset(); eeprom_write(i * sizeof magic, magic, sizeof magic); + } // Read back with single-byte reads for (i = 0; i < 42 * sizeof magic; ++i) { + wdt_reset(); eeprom_read(i, buf, 1); kprintf("EEPROM byte read: %c (%d)\n", buf[0], buf[0]); ASSERT(buf[0] == magic[i % sizeof magic]); @@ -445,6 +341,7 @@ void eeprom_test(void) // Read back again using sequential reads for (i = 0; i < 42; ++i) { + wdt_reset(); memset(buf, 0, sizeof buf); eeprom_read(i * sizeof magic, buf, sizeof magic); kprintf("EEPROM seq read @ 0x%x: '%s'\n", i * sizeof magic, buf);