X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=drv%2Fser_avr.c;h=02a3427e0ac185a3a7be92eac099b67c9ea20965;hb=f52e46baa21748f30f30a9e725edbf90b420ed24;hp=96583e6ecfd4617ae85a89b875b7c57f9b6303f2;hpb=96f8c49fdf97d48ddbacb1d8d94fd5a735051e2d;p=bertos.git diff --git a/drv/ser_avr.c b/drv/ser_avr.c index 96583e6e..02a3427e 100755 --- a/drv/ser_avr.c +++ b/drv/ser_avr.c @@ -1,9 +1,9 @@ -/*! +/** * \file * * * \brief AVR UART and SPI I/O driver @@ -38,6 +38,39 @@ /*#* *#* $Log$ + *#* Revision 1.33 2006/09/13 18:21:24 bernie + *#* Add configurable SPI pin mapping. + *#* + *#* Revision 1.32 2006/07/19 12:56:26 bernie + *#* Convert to new Doxygen style. + *#* + *#* Revision 1.31 2006/05/18 00:37:29 bernie + *#* Use hw_ser.h instead of ubiquitous hw.h. + *#* + *#* Revision 1.30 2006/02/17 22:23:06 bernie + *#* Update POSIX serial emulator. + *#* + *#* Revision 1.29 2005/11/27 23:31:48 bernie + *#* Support avr-libc 1.4. + *#* + *#* Revision 1.28 2005/11/04 16:20:02 bernie + *#* Fix reference to README.devlib in header. + *#* + *#* Revision 1.27 2005/07/03 15:19:31 bernie + *#* Doxygen fix. + *#* + *#* Revision 1.26 2005/04/11 19:10:27 bernie + *#* Include top-level headers from cfg/ subdir. + *#* + *#* Revision 1.25 2005/01/25 08:37:26 bernie + *#* CONFIG_SER_HWHANDSHAKE fixes. + *#* + *#* Revision 1.24 2005/01/14 00:49:16 aleph + *#* Rename callbacks; SerialHardwareVT.txSending: New callback; Add SPI_BUS macros. + *#* + *#* Revision 1.23 2005/01/11 18:09:07 aleph + *#* Add ATmega8 SPI port definitions; Fix transmit complete IRQ bug; add strobe macros to uart1 and spi + *#* *#* Revision 1.22 2004/12/31 17:47:45 bernie *#* Rename UNUSED() to UNUSED_ARG(). *#* @@ -102,37 +135,35 @@ #include "ser.h" #include "ser_p.h" -#include "config.h" -#include "hw.h" /* Required for bus macros overrides */ +#include "hw_ser.h" /* Required for bus macros overrides */ +#include -#include +#include #include #include -#include #include +#if defined(__AVR_LIBC_VERSION__) && (__AVR_LIBC_VERSION__ >= 10400UL) + #include +#else + #include +#endif -/*! - * \name Hardware handshake (RTS/CTS). - * \{ - */ -#ifndef RTS_ON -#define RTS_ON do {} while (0) -#endif -#ifndef RTS_OFF -#define RTS_OFF do {} while (0) -#endif -#ifndef IS_CTS_ON -#define IS_CTS_ON true -#endif -#ifndef EIMSKB_CTS -#define EIMSKB_CTS 0 /*!< Dummy value, must be overridden */ +#if !CONFIG_SER_HWHANDSHAKE + /** + * \name Hardware handshake (RTS/CTS). + * \{ + */ + #define RTS_ON do {} while (0) + #define RTS_OFF do {} while (0) + #define IS_CTS_ON true + #define EIMSKF_CTS 0 /**< Dummy value, must be overridden */ + /*\}*/ #endif -/*\}*/ -/*! +/** * \name Overridable serial bus hooks * * These can be redefined in hw.h to implement @@ -153,7 +184,7 @@ * \{ */ #ifndef SER_UART0_BUS_TXINIT - /*! + /** * Default TXINIT macro - invoked in uart0_init() * * - Enable both the receiver and the transmitter @@ -165,7 +196,7 @@ #endif #ifndef SER_UART0_BUS_TXBEGIN - /*! + /** * Invoked before starting a transmission * * - Enable both the receiver and the transmitter @@ -177,7 +208,7 @@ #endif #ifndef SER_UART0_BUS_TXCHAR - /*! + /** * Invoked to send one character. */ #define SER_UART0_BUS_TXCHAR(c) do { \ @@ -186,7 +217,7 @@ #endif #ifndef SER_UART0_BUS_TXEND - /*! + /** * Invoked as soon as the txfifo becomes empty * * - Keep both the receiver and the transmitter enabled @@ -199,7 +230,7 @@ #endif #ifndef SER_UART0_BUS_TXOFF - /*! + /** * \def SER_UART0_BUS_TXOFF * * Invoked after the last character has been transmitted @@ -212,31 +243,31 @@ #endif #ifndef SER_UART1_BUS_TXINIT - /*! \sa SER_UART0_BUS_TXINIT */ + /** \sa SER_UART0_BUS_TXINIT */ #define SER_UART1_BUS_TXINIT do { \ UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \ } while (0) #endif #ifndef SER_UART1_BUS_TXBEGIN - /*! \sa SER_UART0_BUS_TXBEGIN */ + /** \sa SER_UART0_BUS_TXBEGIN */ #define SER_UART1_BUS_TXBEGIN do { \ UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); \ } while (0) #endif #ifndef SER_UART1_BUS_TXCHAR - /*! \sa SER_UART0_BUS_TXCHAR */ + /** \sa SER_UART0_BUS_TXCHAR */ #define SER_UART1_BUS_TXCHAR(c) do { \ UDR1 = (c); \ } while (0) #endif #ifndef SER_UART1_BUS_TXEND - /*! \sa SER_UART0_BUS_TXEND */ + /** \sa SER_UART0_BUS_TXEND */ #define SER_UART1_BUS_TXEND do { \ UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \ } while (0) #endif #ifndef SER_UART1_BUS_TXOFF - /*! + /** * \def SER_UART1_BUS_TXOFF * * \see SER_UART0_BUS_TXOFF @@ -248,12 +279,50 @@ /*\}*/ +/** + * \name Overridable SPI hooks + * + * These can be redefined in hw.h to implement + * special bus policies such as slave select pin handling, etc. + * + * \{ + */ +#ifndef SER_SPI_BUS_TXINIT + /** + * Default TXINIT macro - invoked in spi_init() + * The default is no action. + */ + #define SER_SPI_BUS_TXINIT +#endif + +#ifndef SER_SPI_BUS_TXCLOSE + /** + * Invoked after the last character has been transmitted. + * The default is no action. + */ + #define SER_SPI_BUS_TXCLOSE +#endif +/*\}*/ + + /* SPI port and pin configuration */ -#define SPI_PORT PORTB -#define SPI_DDR DDRB -#define SPI_SCK_BIT PB1 -#define SPI_MOSI_BIT PB2 -#define SPI_MISO_BIT PB3 +#if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103 + #define SPI_PORT PORTB + #define SPI_DDR DDRB + #define SPI_SS_BIT PB0 + #define SPI_SCK_BIT PB1 + #define SPI_MOSI_BIT PB2 + #define SPI_MISO_BIT PB3 +#elif CPU_AVR_ATMEGA8 + #define SPI_PORT PORTB + #define SPI_DDR DDRB + #define SPI_SS_BIT PB2 + #define SPI_SCK_BIT PB5 + #define SPI_MOSI_BIT PB3 + #define SPI_MISO_BIT PB4 +#else + #error Unknown architecture +#endif /* USART register definitions */ #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 @@ -268,6 +337,7 @@ #define UBRR0H UBRRH #define SIG_UART0_DATA SIG_UART_DATA #define SIG_UART0_RECV SIG_UART_RECV + #define SIG_UART0_TRANS SIG_UART_TRANS #elif CPU_AVR_ATMEGA103 #define AVR_HAS_UART1 0 #define UCSR0B UCR @@ -276,12 +346,13 @@ #define UBRR0L UBRR #define SIG_UART0_DATA SIG_UART_DATA #define SIG_UART0_RECV SIG_UART_RECV + #define SIG_UART0_TRANS SIG_UART_TRANS #else #error Unknown architecture #endif -/*! +/** * \def CONFIG_SER_STROBE * * This is a debug facility that can be used to @@ -312,7 +383,7 @@ static unsigned char spi_txbuffer[CONFIG_SPI_TXBUFSIZE]; static unsigned char spi_rxbuffer[CONFIG_SPI_RXBUFSIZE]; -/*! +/** * Internal hardware state structure * * The \a sending variable is true while the transmission @@ -359,6 +430,7 @@ static void uart0_init( { SER_UART0_BUS_TXINIT; RTS_ON; + SER_STROBE_INIT; } static void uart0_cleanup(UNUSED_ARG(struct SerialHardware *, _hw)) @@ -387,7 +459,7 @@ static void uart0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned /* Compute baud-rate period */ uint16_t period = (((CLOCK_FREQ / 16UL) + (rate / 2)) / rate) - 1; -#ifndef __AVR_ATmega103__ +#if !CPU_AVR_ATMEGA103 UBRR0H = (period) >> 8; #endif UBRR0L = (period); @@ -468,17 +540,73 @@ static void spi_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct * with the KBus serial RX, and the transmitter of the slave boards * would be unable to drive the line. */ - SPI_DDR |= BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT); - SPI_DDR &= ~BV(SPI_MISO_BIT); - /* Enable SPI, IRQ on, Master, CPU_CLOCK/16 */ - SPCR = BV(SPE) | BV(SPIE) | BV(MSTR) | BV(SPR0); + ATOMIC(SPI_DDR |= (BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT))); + + /* + * If the SPI master mode is activated and the SS pin is in input and tied low, + * the SPI hardware will automatically switch to slave mode! + * For proper communication this pins should therefore be: + * - as output + * - as input but tied high forever! + * This driver set the pin as output. + */ + #warning SPI SS pin set as output for proper operation, check schematics for possible conflicts. + ATOMIC(SPI_DDR |= BV(SPI_SS_BIT)); + + ATOMIC(SPI_DDR &= ~BV(SPI_MISO_BIT)); + /* Enable SPI, IRQ on, Master */ + SPCR = BV(SPE) | BV(SPIE) | BV(MSTR); + + /* Set data order */ + #if CONFIG_SPI_DATA_ORDER == SER_LSB_FIRST + SPCR |= BV(DORD); + #endif + + /* Set SPI clock rate */ + #if CONFIG_SPI_CLOCK_DIV == 128 + SPCR |= (BV(SPR1) | BV(SPR0)); + #elif (CONFIG_SPI_CLOCK_DIV == 64 || CONFIG_SPI_CLOCK_DIV == 32) + SPCR |= BV(SPR1); + #elif (CONFIG_SPI_CLOCK_DIV == 16 || CONFIG_SPI_CLOCK_DIV == 8) + SPCR |= BV(SPR0); + #elif (CONFIG_SPI_CLOCK_DIV == 4 || CONFIG_SPI_CLOCK_DIV == 2) + // SPR0 & SDPR1 both at 0 + #else + #error Unsupported SPI clock division factor. + #endif + + /* Set SPI2X bit (spi double frequency) */ + #if (CONFIG_SPI_CLOCK_DIV == 128 || CONFIG_SPI_CLOCK_DIV == 64 \ + || CONFIG_SPI_CLOCK_DIV == 16 || CONFIG_SPI_CLOCK_DIV == 4) + SPSR &= ~BV(SPI2X); + #elif (CONFIG_SPI_CLOCK_DIV == 32 || CONFIG_SPI_CLOCK_DIV == 8 || CONFIG_SPI_CLOCK_DIV == 2) + SPSR |= BV(SPI2X); + #else + #error Unsupported SPI clock division factor. + #endif + + /* Set clock polarity */ + #if CONFIG_SPI_CLOCK_POL == 1 + SPCR |= BV(CPOL); + #endif + + /* Set clock phase */ + #if CONFIG_SPI_CLOCK_PHASE == 1 + SPCR |= BV(CPHA); + #endif + SER_SPI_BUS_TXINIT; + + SER_STROBE_INIT; } static void spi_cleanup(UNUSED_ARG(struct SerialHardware *, _hw)) { SPCR = 0; + + SER_SPI_BUS_TXCLOSE; + /* Set all pins as inputs */ - SPI_DDR &= ~(BV(SPI_MISO_BIT) | BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT)); + ATOMIC(SPI_DDR &= ~(BV(SPI_MISO_BIT) | BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT) | BV(SPI_SS_BIT))); } static void spi_starttx(struct SerialHardware *_hw) @@ -510,6 +638,13 @@ static void spi_setparity(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(i // nop } +static bool tx_sending(struct SerialHardware* _hw) +{ + struct AvrSerial *hw = (struct AvrSerial *)_hw; + return hw->sending; +} + + // FIXME: move into compiler.h? Ditch? #if COMPILER_C99 @@ -528,9 +663,10 @@ static const struct SerialHardwareVT UART0_VT = { C99INIT(init, uart0_init), C99INIT(cleanup, uart0_cleanup), - C99INIT(setbaudrate, uart0_setbaudrate), - C99INIT(setparity, uart0_setparity), - C99INIT(enabletxirq, uart0_enabletxirq), + C99INIT(setBaudrate, uart0_setbaudrate), + C99INIT(setParity, uart0_setparity), + C99INIT(txStart, uart0_enabletxirq), + C99INIT(txSending, tx_sending), }; #if AVR_HAS_UART1 @@ -538,9 +674,10 @@ static const struct SerialHardwareVT UART1_VT = { C99INIT(init, uart1_init), C99INIT(cleanup, uart1_cleanup), - C99INIT(setbaudrate, uart1_setbaudrate), - C99INIT(setparity, uart1_setparity), - C99INIT(enabletxirq, uart1_enabletxirq), + C99INIT(setBaudrate, uart1_setbaudrate), + C99INIT(setParity, uart1_setparity), + C99INIT(txStart, uart1_enabletxirq), + C99INIT(txSending, tx_sending), }; #endif // AVR_HAS_UART1 @@ -548,9 +685,10 @@ static const struct SerialHardwareVT SPI_VT = { C99INIT(init, spi_init), C99INIT(cleanup, spi_cleanup), - C99INIT(setbaudrate, spi_setbaudrate), - C99INIT(setparity, spi_setparity), - C99INIT(enabletxirq, spi_starttx), + C99INIT(setBaudrate, spi_setbaudrate), + C99INIT(setParity, spi_setparity), + C99INIT(txStart, spi_starttx), + C99INIT(txSending, tx_sending), }; static struct AvrSerial UARTDescs[SER_CNT] = @@ -589,7 +727,7 @@ static struct AvrSerial UARTDescs[SER_CNT] = } }; -struct SerialHardware* ser_hw_getdesc(int unit) +struct SerialHardware *ser_hw_getdesc(int unit) { ASSERT(unit < SER_CNT); return &UARTDescs[unit].hw; @@ -602,18 +740,18 @@ struct SerialHardware* ser_hw_getdesc(int unit) #if CONFIG_SER_HWHANDSHAKE -//! This interrupt is triggered when the CTS line goes high +/// This interrupt is triggered when the CTS line goes high SIGNAL(SIG_CTS) { // Re-enable UDR empty interrupt and TX, then disable CTS interrupt UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); - cbi(EIMSK, EIMSKB_CTS); + EIMSK &= ~EIMSKF_CTS; } #endif // CONFIG_SER_HWHANDSHAKE -/*! +/** * Serial 0 TX interrupt handler */ SIGNAL(SIG_UART0_DATA) @@ -635,8 +773,8 @@ SIGNAL(SIG_UART0_DATA) // Disable rx interrupt and tx, enable CTS interrupt // UNTESTED UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN); - sbi(EIFR, EIMSKB_CTS); - sbi(EIMSK, EIMSKB_CTS); + EIFR |= EIMSKF_CTS; + EIMSK |= EIMSKF_CTS; } #endif else @@ -649,7 +787,7 @@ SIGNAL(SIG_UART0_DATA) } #ifdef SER_UART0_BUS_TXOFF -/*! +/** * Serial port 0 TX complete interrupt handler. * * This IRQ is usually disabled. The UDR-empty interrupt @@ -684,7 +822,7 @@ SIGNAL(SIG_UART0_TRANS) #if AVR_HAS_UART1 -/*! +/** * Serial 1 TX interrupt handler */ SIGNAL(SIG_UART1_DATA) @@ -706,8 +844,8 @@ SIGNAL(SIG_UART1_DATA) // Disable rx interrupt and tx, enable CTS interrupt // UNTESTED UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); - sbi(EIFR, EIMSKB_CTS); - sbi(EIMSK, EIMSKB_CTS); + EIFR |= EIMSKF_CTS; + EIMSK |= EIMSKF_CTS; } #endif else @@ -720,7 +858,7 @@ SIGNAL(SIG_UART1_DATA) } #ifdef SER_UART1_BUS_TXOFF -/*! +/** * Serial port 1 TX complete interrupt handler. * * \sa port 0 TX complete handler. @@ -745,7 +883,7 @@ SIGNAL(SIG_UART1_TRANS) #endif // AVR_HAS_UART1 -/*! +/** * Serial 0 RX complete interrupt handler. * * This handler is interruptible. @@ -799,7 +937,7 @@ SIGNAL(SIG_UART0_RECV) #if AVR_HAS_UART1 -/*! +/** * Serial 1 RX complete interrupt handler. * * This handler is interruptible. @@ -848,11 +986,13 @@ SIGNAL(SIG_UART1_RECV) #endif // AVR_HAS_UART1 -/*! +/** * SPI interrupt handler */ SIGNAL(SIG_SPI) { + SER_STROBE_ON; + /* Read incoming byte. */ if (!fifo_isfull(&ser_spi->rxfifo)) fifo_push(&ser_spi->rxfifo, SPDR); @@ -867,4 +1007,6 @@ SIGNAL(SIG_SPI) SPDR = fifo_pop(&ser_spi->txfifo); else UARTDescs[SER_SPI].sending = false; + + SER_STROBE_OFF; }