X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=drv%2Fser_avr.c;h=1176659640d1e926864a0866f49899a73be7b28b;hb=46ac2c9347e738ee3c23109b83d522023ac4e7c9;hp=05c93943cb020c223f263fbee8c1dd639ea5a41e;hpb=243b4bcd1563bfca887b9534a6abb7249683d819;p=bertos.git diff --git a/drv/ser_avr.c b/drv/ser_avr.c index 05c93943..11766596 100755 --- a/drv/ser_avr.c +++ b/drv/ser_avr.c @@ -1,9 +1,9 @@ -/*! +/** * \file * * * \brief AVR UART and SPI I/O driver @@ -38,6 +38,33 @@ /*#* *#* $Log$ + *#* Revision 1.34 2006/11/23 13:19:02 batt + *#* Add support for ATmega1281. + *#* + *#* Revision 1.33 2006/09/13 18:21:24 bernie + *#* Add configurable SPI pin mapping. + *#* + *#* Revision 1.32 2006/07/19 12:56:26 bernie + *#* Convert to new Doxygen style. + *#* + *#* Revision 1.31 2006/05/18 00:37:29 bernie + *#* Use hw_ser.h instead of ubiquitous hw.h. + *#* + *#* Revision 1.30 2006/02/17 22:23:06 bernie + *#* Update POSIX serial emulator. + *#* + *#* Revision 1.29 2005/11/27 23:31:48 bernie + *#* Support avr-libc 1.4. + *#* + *#* Revision 1.28 2005/11/04 16:20:02 bernie + *#* Fix reference to README.devlib in header. + *#* + *#* Revision 1.27 2005/07/03 15:19:31 bernie + *#* Doxygen fix. + *#* + *#* Revision 1.26 2005/04/11 19:10:27 bernie + *#* Include top-level headers from cfg/ subdir. + *#* *#* Revision 1.25 2005/01/25 08:37:26 bernie *#* CONFIG_SER_HWHANDSHAKE fixes. *#* @@ -111,31 +138,59 @@ #include "ser.h" #include "ser_p.h" -#include "config.h" -#include "hw.h" /* Required for bus macros overrides */ -#include +#include /* Required for bus macros overrides */ +#include /* CLOCK_FREQ */ +#include + +#include #include #include -#include #include +#if defined(__AVR_LIBC_VERSION__) && (__AVR_LIBC_VERSION__ >= 10400UL) + #include +#else + #include +#endif #if !CONFIG_SER_HWHANDSHAKE - /*! + /** * \name Hardware handshake (RTS/CTS). * \{ */ #define RTS_ON do {} while (0) #define RTS_OFF do {} while (0) #define IS_CTS_ON true - #define EIMSKF_CTS 0 /*!< Dummy value, must be overridden */ + #define EIMSKF_CTS 0 /**< Dummy value, must be overridden */ /*\}*/ #endif +#if CPU_AVR_ATMEGA1281 + #define BIT_RXCIE0 RXCIE0 + #define BIT_RXEN0 RXEN0 + #define BIT_TXEN0 TXEN0 + #define BIT_UDRIE0 UDRIE0 + + #define BIT_RXCIE1 RXCIE1 + #define BIT_RXEN1 RXEN1 + #define BIT_TXEN1 TXEN1 + #define BIT_UDRIE1 UDRIE1 +#else + #define BIT_RXCIE0 RXCIE + #define BIT_RXEN0 RXEN + #define BIT_TXEN0 TXEN + #define BIT_UDRIE0 UDRIE + + #define BIT_RXCIE1 RXCIE + #define BIT_RXEN1 RXEN + #define BIT_TXEN1 TXEN + #define BIT_UDRIE1 UDRIE +#endif + -/*! +/** * \name Overridable serial bus hooks * * These can be redefined in hw.h to implement @@ -156,31 +211,31 @@ * \{ */ #ifndef SER_UART0_BUS_TXINIT - /*! + /** * Default TXINIT macro - invoked in uart0_init() * * - Enable both the receiver and the transmitter * - Enable only the RX complete interrupt */ #define SER_UART0_BUS_TXINIT do { \ - UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \ + UCSR0B = BV(BIT_RXCIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0); \ } while (0) #endif #ifndef SER_UART0_BUS_TXBEGIN - /*! + /** * Invoked before starting a transmission * * - Enable both the receiver and the transmitter * - Enable both the RX complete and UDR empty interrupts */ #define SER_UART0_BUS_TXBEGIN do { \ - UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); \ + UCSR0B = BV(BIT_RXCIE0) | BV(BIT_UDRIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0); \ } while (0) #endif #ifndef SER_UART0_BUS_TXCHAR - /*! + /** * Invoked to send one character. */ #define SER_UART0_BUS_TXCHAR(c) do { \ @@ -189,7 +244,7 @@ #endif #ifndef SER_UART0_BUS_TXEND - /*! + /** * Invoked as soon as the txfifo becomes empty * * - Keep both the receiver and the transmitter enabled @@ -197,12 +252,12 @@ * - Disable the UDR empty interrupt */ #define SER_UART0_BUS_TXEND do { \ - UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \ + UCSR0B = BV(BIT_RXCIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0); \ } while (0) #endif #ifndef SER_UART0_BUS_TXOFF - /*! + /** * \def SER_UART0_BUS_TXOFF * * Invoked after the last character has been transmitted @@ -215,31 +270,31 @@ #endif #ifndef SER_UART1_BUS_TXINIT - /*! \sa SER_UART0_BUS_TXINIT */ + /** \sa SER_UART0_BUS_TXINIT */ #define SER_UART1_BUS_TXINIT do { \ - UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \ + UCSR1B = BV(BIT_RXCIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1); \ } while (0) #endif #ifndef SER_UART1_BUS_TXBEGIN - /*! \sa SER_UART0_BUS_TXBEGIN */ + /** \sa SER_UART0_BUS_TXBEGIN */ #define SER_UART1_BUS_TXBEGIN do { \ - UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); \ + UCSR1B = BV(BIT_RXCIE1) | BV(BIT_UDRIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1); \ } while (0) #endif #ifndef SER_UART1_BUS_TXCHAR - /*! \sa SER_UART0_BUS_TXCHAR */ + /** \sa SER_UART0_BUS_TXCHAR */ #define SER_UART1_BUS_TXCHAR(c) do { \ UDR1 = (c); \ } while (0) #endif #ifndef SER_UART1_BUS_TXEND - /*! \sa SER_UART0_BUS_TXEND */ + /** \sa SER_UART0_BUS_TXEND */ #define SER_UART1_BUS_TXEND do { \ - UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \ + UCSR1B = BV(BIT_RXCIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1); \ } while (0) #endif #ifndef SER_UART1_BUS_TXOFF - /*! + /** * \def SER_UART1_BUS_TXOFF * * \see SER_UART0_BUS_TXOFF @@ -251,7 +306,7 @@ /*\}*/ -/*! +/** * \name Overridable SPI hooks * * These can be redefined in hw.h to implement @@ -260,9 +315,7 @@ * \{ */ #ifndef SER_SPI_BUS_TXINIT - /*! - * \def SER_SPI_BUS_TXINIT - * + /** * Default TXINIT macro - invoked in spi_init() * The default is no action. */ @@ -270,9 +323,7 @@ #endif #ifndef SER_SPI_BUS_TXCLOSE - /*! - * \def SER_SPI_BUS_TXCLOSE - * + /** * Invoked after the last character has been transmitted. * The default is no action. */ @@ -282,15 +333,17 @@ /* SPI port and pin configuration */ -#if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103 +#if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103 || CPU_AVR_ATMEGA1281 #define SPI_PORT PORTB #define SPI_DDR DDRB + #define SPI_SS_BIT PB0 #define SPI_SCK_BIT PB1 #define SPI_MOSI_BIT PB2 #define SPI_MISO_BIT PB3 #elif CPU_AVR_ATMEGA8 #define SPI_PORT PORTB #define SPI_DDR DDRB + #define SPI_SS_BIT PB2 #define SPI_SCK_BIT PB5 #define SPI_MOSI_BIT PB3 #define SPI_MISO_BIT PB4 @@ -299,7 +352,7 @@ #endif /* USART register definitions */ -#if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 +#if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA1281 #define AVR_HAS_UART1 1 #elif CPU_AVR_ATMEGA8 #define AVR_HAS_UART1 0 @@ -326,7 +379,7 @@ #endif -/*! +/** * \def CONFIG_SER_STROBE * * This is a debug facility that can be used to @@ -357,7 +410,7 @@ static unsigned char spi_txbuffer[CONFIG_SPI_TXBUFSIZE]; static unsigned char spi_rxbuffer[CONFIG_SPI_RXBUFSIZE]; -/*! +/** * Internal hardware state structure * * The \a sending variable is true while the transmission @@ -444,7 +497,7 @@ static void uart0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned static void uart0_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity) { #if !CPU_AVR_ATMEGA103 - UCSR0C = (UCSR0C & ~(BV(UPM1) | BV(UPM0))) | ((parity) << UPM0); + UCSR0C = (UCSR0C & ~(BV(UPM01) | BV(UPM00))) | ((parity) << UPM00); #endif } @@ -494,7 +547,7 @@ static void uart1_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned static void uart1_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity) { - UCSR1C = (UCSR1C & ~(BV(UPM1) | BV(UPM0))) | ((parity) << UPM0); + UCSR1C = (UCSR1C & ~(BV(UPM11) | BV(UPM10))) | ((parity) << UPM10); } #endif // AVR_HAS_UART1 @@ -514,11 +567,60 @@ static void spi_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct * with the KBus serial RX, and the transmitter of the slave boards * would be unable to drive the line. */ - SPI_DDR |= BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT); - SPI_DDR &= ~BV(SPI_MISO_BIT); - /* Enable SPI, IRQ on, Master, CPU_CLOCK/16 */ - SPCR = BV(SPE) | BV(SPIE) | BV(MSTR) | BV(SPR0); + ATOMIC(SPI_DDR |= (BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT))); + + /* + * If the SPI master mode is activated and the SS pin is in input and tied low, + * the SPI hardware will automatically switch to slave mode! + * For proper communication this pins should therefore be: + * - as output + * - as input but tied high forever! + * This driver set the pin as output. + */ + #warning SPI SS pin set as output for proper operation, check schematics for possible conflicts. + ATOMIC(SPI_DDR |= BV(SPI_SS_BIT)); + + ATOMIC(SPI_DDR &= ~BV(SPI_MISO_BIT)); + /* Enable SPI, IRQ on, Master */ + SPCR = BV(SPE) | BV(SPIE) | BV(MSTR); + + /* Set data order */ + #if CONFIG_SPI_DATA_ORDER == SER_LSB_FIRST + SPCR |= BV(DORD); + #endif + + /* Set SPI clock rate */ + #if CONFIG_SPI_CLOCK_DIV == 128 + SPCR |= (BV(SPR1) | BV(SPR0)); + #elif (CONFIG_SPI_CLOCK_DIV == 64 || CONFIG_SPI_CLOCK_DIV == 32) + SPCR |= BV(SPR1); + #elif (CONFIG_SPI_CLOCK_DIV == 16 || CONFIG_SPI_CLOCK_DIV == 8) + SPCR |= BV(SPR0); + #elif (CONFIG_SPI_CLOCK_DIV == 4 || CONFIG_SPI_CLOCK_DIV == 2) + // SPR0 & SDPR1 both at 0 + #else + #error Unsupported SPI clock division factor. + #endif + + /* Set SPI2X bit (spi double frequency) */ + #if (CONFIG_SPI_CLOCK_DIV == 128 || CONFIG_SPI_CLOCK_DIV == 64 \ + || CONFIG_SPI_CLOCK_DIV == 16 || CONFIG_SPI_CLOCK_DIV == 4) + SPSR &= ~BV(SPI2X); + #elif (CONFIG_SPI_CLOCK_DIV == 32 || CONFIG_SPI_CLOCK_DIV == 8 || CONFIG_SPI_CLOCK_DIV == 2) + SPSR |= BV(SPI2X); + #else + #error Unsupported SPI clock division factor. + #endif + + /* Set clock polarity */ + #if CONFIG_SPI_CLOCK_POL == 1 + SPCR |= BV(CPOL); + #endif + /* Set clock phase */ + #if CONFIG_SPI_CLOCK_PHASE == 1 + SPCR |= BV(CPHA); + #endif SER_SPI_BUS_TXINIT; SER_STROBE_INIT; @@ -531,7 +633,7 @@ static void spi_cleanup(UNUSED_ARG(struct SerialHardware *, _hw)) SER_SPI_BUS_TXCLOSE; /* Set all pins as inputs */ - SPI_DDR &= ~(BV(SPI_MISO_BIT) | BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT)); + ATOMIC(SPI_DDR &= ~(BV(SPI_MISO_BIT) | BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT) | BV(SPI_SS_BIT))); } static void spi_starttx(struct SerialHardware *_hw) @@ -652,7 +754,7 @@ static struct AvrSerial UARTDescs[SER_CNT] = } }; -struct SerialHardware* ser_hw_getdesc(int unit) +struct SerialHardware *ser_hw_getdesc(int unit) { ASSERT(unit < SER_CNT); return &UARTDescs[unit].hw; @@ -665,7 +767,7 @@ struct SerialHardware* ser_hw_getdesc(int unit) #if CONFIG_SER_HWHANDSHAKE -//! This interrupt is triggered when the CTS line goes high +/// This interrupt is triggered when the CTS line goes high SIGNAL(SIG_CTS) { // Re-enable UDR empty interrupt and TX, then disable CTS interrupt @@ -676,10 +778,10 @@ SIGNAL(SIG_CTS) #endif // CONFIG_SER_HWHANDSHAKE -/*! +/** * Serial 0 TX interrupt handler */ -SIGNAL(SIG_UART0_DATA) +SIGNAL(USART0_UDRE_vect) { SER_STROBE_ON; @@ -712,7 +814,7 @@ SIGNAL(SIG_UART0_DATA) } #ifdef SER_UART0_BUS_TXOFF -/*! +/** * Serial port 0 TX complete interrupt handler. * * This IRQ is usually disabled. The UDR-empty interrupt @@ -747,10 +849,10 @@ SIGNAL(SIG_UART0_TRANS) #if AVR_HAS_UART1 -/*! +/** * Serial 1 TX interrupt handler */ -SIGNAL(SIG_UART1_DATA) +SIGNAL(USART1_UDRE_vect) { SER_STROBE_ON; @@ -783,7 +885,7 @@ SIGNAL(SIG_UART1_DATA) } #ifdef SER_UART1_BUS_TXOFF -/*! +/** * Serial port 1 TX complete interrupt handler. * * \sa port 0 TX complete handler. @@ -808,7 +910,7 @@ SIGNAL(SIG_UART1_TRANS) #endif // AVR_HAS_UART1 -/*! +/** * Serial 0 RX complete interrupt handler. * * This handler is interruptible. @@ -823,7 +925,7 @@ SIGNAL(SIG_UART1_TRANS) * RXCIE is cleared. Unfortunately the RXC flag is read-only * and can't be cleared by code. */ -SIGNAL(SIG_UART0_RECV) +SIGNAL(USART0_RX_vect) { SER_STROBE_ON; @@ -862,7 +964,7 @@ SIGNAL(SIG_UART0_RECV) #if AVR_HAS_UART1 -/*! +/** * Serial 1 RX complete interrupt handler. * * This handler is interruptible. @@ -871,9 +973,9 @@ SIGNAL(SIG_UART0_RECV) * is heavily loaded, because an interrupt could be retriggered * when executing the handler prologue before RXCIE is disabled. * - * \see SIGNAL(SIG_UART0_RECV) + * \see SIGNAL(USART1_RX_vect) */ -SIGNAL(SIG_UART1_RECV) +SIGNAL(USART1_RX_vect) { SER_STROBE_ON; @@ -911,7 +1013,7 @@ SIGNAL(SIG_UART1_RECV) #endif // AVR_HAS_UART1 -/*! +/** * SPI interrupt handler */ SIGNAL(SIG_SPI)