X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=drv%2Fser_avr.c;h=9014cccf5fdbc7168079b4176fd4963a3c8b6faf;hb=be670d92a85770cfa7edcbaca9a94032ddf1b114;hp=c43f7238b70763937b905dfdb9a22a4e56d4ae6f;hpb=22240d0455c6bd837fe928b29068e795be3febae;p=bertos.git diff --git a/drv/ser_avr.c b/drv/ser_avr.c index c43f7238..9014cccf 100755 --- a/drv/ser_avr.c +++ b/drv/ser_avr.c @@ -1,8 +1,8 @@ /*! * \file * * @@ -36,45 +36,65 @@ * \author Stefano Fedrigo */ -/* - * $Log$ - * Revision 1.9 2004/08/02 20:20:29 aleph - * Merge from project_ks - * - * Revision 1.8 2004/07/29 22:57:09 bernie - * Several tweaks to reduce code size on ATmega8. - * - * Revision 1.7 2004/07/18 21:54:23 bernie - * Add ATmega8 support. - * - * Revision 1.5 2004/06/27 15:25:40 aleph - * Add missing callbacks for SPI; - * Change UNUSED() macro to new version with two args; - * Use TX line filling only on the correct KBUS serial port; - * Fix nasty IRQ disabling bug in recv complete hander for port 1. - * - * Revision 1.4 2004/06/03 11:27:09 bernie - * Add dual-license information. - * - * Revision 1.3 2004/06/02 21:35:24 aleph - * Serial enhancements: interruptible receive handler and 8 bit serial status for AVR; remove volatile attribute to FIFOBuffer, useless for new fifobuf routens - * - * Revision 1.2 2004/05/23 18:21:53 bernie - * Trim CVS logs and cleanup header info. - * - */ +/*#* + *#* $Log$ + *#* Revision 1.15 2004/09/14 21:05:36 bernie + *#* Use debug.h instead of kdebug.h; Use new AVR pin names; Spelling fixes. + *#* + *#* Revision 1.14 2004/09/06 21:50:00 bernie + *#* Spelling fixes. + *#* + *#* Revision 1.13 2004/09/06 21:40:50 bernie + *#* Move buffer handling in chip-specific driver. + *#* + *#* Revision 1.12 2004/08/29 22:06:10 bernie + *#* Fix a bug in the (unused) RTS/CTS code; Clarify documentation. + *#* + *#* Revision 1.10 2004/08/10 06:30:41 bernie + *#* Major redesign of serial bus policy handling. + *#* + *#* Revision 1.9 2004/08/02 20:20:29 aleph + *#* Merge from project_ks + *#* + *#* Revision 1.8 2004/07/29 22:57:09 bernie + *#* Several tweaks to reduce code size on ATmega8. + *#* + *#* Revision 1.7 2004/07/18 21:54:23 bernie + *#* Add ATmega8 support. + *#* + *#* Revision 1.5 2004/06/27 15:25:40 aleph + *#* Add missing callbacks for SPI; + *#* Change UNUSED() macro to new version with two args; + *#* Use TX line filling only on the correct KBUS serial port; + *#* Fix nasty IRQ disabling bug in recv complete hander for port 1. + *#* + *#* Revision 1.4 2004/06/03 11:27:09 bernie + *#* Add dual-license information. + *#* + *#* Revision 1.3 2004/06/02 21:35:24 aleph + *#* Serial enhancements: interruptible receive handler and 8 bit serial status for AVR; remove volatile attribute to FIFOBuffer, useless for new fifobuf routens + *#* + *#* Revision 1.2 2004/05/23 18:21:53 bernie + *#* Trim CVS logs and cleanup header info. + *#* + *#*/ #include "ser.h" #include "ser_p.h" -#include "kdebug.h" #include "config.h" -#include "hw.h" +#include "hw.h" /* Required for bus macros overrides */ + +#include +#include #include #include -/* Hardware handshake (RTS/CTS). */ +/*! + * \name Hardware handshake (RTS/CTS). + * \{ + */ #ifndef RTS_ON #define RTS_ON do {} while (0) #endif @@ -84,40 +104,130 @@ #ifndef IS_CTS_ON #define IS_CTS_ON true #endif +#ifndef EIMSKB_CTS +#define EIMSKB_CTS 0 /*!< Dummy value, must be overridden */ +#endif +/*\}*/ + + +/*! + * \name Overridable serial bus hooks + * + * These can be redefined in hw.h to implement + * special bus policies such as half-duplex, 485, etc. + * + * + * \code + * TXBEGIN TXCHAR TXEND TXOFF + * | __________|__________ | | + * | | | | | | | | | + * v v v v v v v v v + * ______ __ __ __ __ __ __ ________________ + * \/ \/ \/ \/ \/ \/ \/ + * ______/\__/\__/\__/\__/\__/\__/ + * + * \endcode + * + * \{ + */ +#ifndef SER_UART0_BUS_TXINIT + /*! + * Default TXINIT macro - invoked in uart0_init() + * + * - Enable both the receiver and the transmitter + * - Enable only the RX complete interrupt + */ + #define SER_UART0_BUS_TXINIT do { \ + UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \ + } while (0) +#endif + +#ifndef SER_UART0_BUS_TXBEGIN + /*! + * Invoked before starting a transmission + * + * - Enable both the receiver and the transmitter + * - Enable both the RX complete and UDR empty interrupts + */ + #define SER_UART0_BUS_TXBEGIN do { \ + UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); \ + } while (0) +#endif + +#ifndef SER_UART0_BUS_TXCHAR + /*! + * Invoked to send one character. + */ + #define SER_UART0_BUS_TXCHAR(c) do { \ + UDR0 = (c); \ + } while (0) +#endif -/* External 485 transceiver on UART0 (to be overridden in "hw.h"). */ -#if !defined(SER_UART0_485_INIT) - #if defined(SER_UART0_485_RX) || defined(SER_UART0_485_TX) - #error SER_UART0_485_INIT, SER_UART0_485_RX and SER_UART0_485_TX must be defined together - #endif - #define SER_UART0_485_INIT do {} while (0) - #define SER_UART0_485_TX do {} while (0) - /* SER_UART0_485_RX must not be defined! */ -#elif !defined(SER_UART0_485_RX) || !defined(SER_UART0_485_TX) - #error SER_UART0_485_INIT, SER_UART0_485_RX and SER_UART0_485_TX must be defined together +#ifndef SER_UART0_BUS_TXEND + /*! + * Invoked as soon as the txfifo becomes empty + * + * - Keep both the receiver and the transmitter enabled + * - Keep the RX complete interrupt enabled + * - Disable the UDR empty interrupt + */ + #define SER_UART0_BUS_TXEND do { \ + UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \ + } while (0) +#endif + +#ifndef SER_UART0_BUS_TXOFF + /*! + * \def SER_UART0_BUS_TXOFF + * + * Invoked after the last character has been transmitted + * + * The default is no action. + */ #endif -/* External 485 transceiver on UART1 (to be overridden in "hw.h"). */ -#ifndef SER_UART1_485_INIT - #if defined(SER_UART1_485_RX) || defined(SER_UART1_485_TX) - #error SER_UART1_485_INIT, SER_UART1_485_RX and SER_UART1_485_TX must be defined together - #endif - #define SER_UART1_485_INIT do {} while (0) - #define SER_UART1_485_TX do {} while (0) - /* SER_UART1_485_RX must not be defined! */ -#elif !defined(SER_UART1_485_RX) || !defined(SER_UART1_485_TX) - #error SER_UART1_485_INIT, SER_UART1_485_RX and SER_UART1_485_TX must be defined together +#ifndef SER_UART1_BUS_TXINIT + /*! \sa SER_UART0_BUS_TXINIT */ + #define SER_UART1_BUS_TXINIT do { \ + UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \ + } while (0) #endif +#ifndef SER_UART1_BUS_TXBEGIN + /*! \sa SER_UART0_BUS_TXBEGIN */ + #define SER_UART1_BUS_TXBEGIN do { \ + UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); \ + } while (0) +#endif +#ifndef SER_UART1_BUS_TXCHAR + /*! \sa SER_UART0_BUS_TXCHAR */ + #define SER_UART1_BUS_TXCHAR(c) do { \ + UDR1 = (c); \ + } while (0) +#endif +#ifndef SER_UART1_BUS_TXEND + /*! \sa SER_UART0_BUS_TXEND */ + #define SER_UART1_BUS_TXEND do { \ + UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \ + } while (0) +#endif +#ifndef SER_UART1_BUS_TXOFF + /*! + * \def SER_UART1_BUS_TXOFF + * + * \see SER_UART0_BUS_TXOFF + */ +#endif +/*\}*/ /* SPI port and pin configuration */ #define SPI_PORT PORTB #define SPI_DDR DDRB -#define SPI_SCK_BIT PORTB1 -#define SPI_MOSI_BIT PORTB2 -#define SPI_MISO_BIT PORTB3 - +#define SPI_SCK_BIT PB1 +#define SPI_MOSI_BIT PB2 +#define SPI_MISO_BIT PB3 +/* USART registers definitions */ #if defined(__AVR_ATmega64__) || defined(__AVR_ATmega128__) #define AVR_HAS_UART1 1 #elif defined(__AVR_ATmega8__) @@ -143,13 +253,60 @@ #endif -/* Transmission fill byte */ -#define SER_FILL_BYTE 0xAA +/*! + * \def CONFIG_SER_STROBE + * + * This is a debug facility that can be used to + * monitor SER interrupt activity on an external pin. + * + * To use strobes, redefine the macros SER_STROBE_ON, + * SER_STROBE_OFF and SER_STROBE_INIT and set + * CONFIG_SER_STROBE to 1. + */ +#if !defined(CONFIG_SER_STROBE) || !CONFIG_SER_STROBE + #define SER_STROBE_ON do {/*nop*/} while(0) + #define SER_STROBE_OFF do {/*nop*/} while(0) + #define SER_STROBE_INIT do {/*nop*/} while(0) +#endif /* From the high-level serial driver */ extern struct Serial ser_handles[SER_CNT]; +/* TX and RX buffers */ +static unsigned char uart0_txbuffer[CONFIG_UART0_TXBUFSIZE]; +static unsigned char uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE]; +#if AVR_HAS_UART1 + static unsigned char uart1_txbuffer[CONFIG_UART1_TXBUFSIZE]; + static unsigned char uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE]; +#endif +static unsigned char spi_txbuffer[CONFIG_SPI_TXBUFSIZE]; +static unsigned char spi_rxbuffer[CONFIG_SPI_RXBUFSIZE]; + + +/*! + * Internal hardware state structure + * + * The \a sending variable is true while the transmission + * interrupt is retriggering itself. + * + * For the USARTs the \a sending flag is useful for taking specific + * actions before sending a burst of data, at the start of a trasmission + * but not before every char sent. + * + * For the SPI, this flag is necessary because the SPI sends and receives + * bytes at the same time and the SPI IRQ is unique for send/receive. + * The only way to start transmission is to write data in SPDR (this + * is done by spi_starttx()). We do this *only* if a transfer is + * not already started. + */ +struct AvrSerial +{ + struct SerialHardware hw; + volatile bool sending; +}; + + /* * These are to trick GCC into *not* using * absolute addressing mode when accessing @@ -165,47 +322,13 @@ struct Serial *ser_uart1 = &ser_handles[SER_UART1]; struct Serial *ser_spi = &ser_handles[SER_SPI]; -static void uart0_enabletxirq(UNUSED(struct SerialHardware *, ctx)) -{ -#if CONFIG_SER_TXFILL && (CONFIG_KBUS_PORT == 0) - UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN) | BV(UCSZ2); -#elif defined(SER_UART0_485_TX) - /* Disable receiver, enable transmitter, switch 485 transceiver. */ - UCSR0B = BV(UDRIE) | BV(TXEN); - SER_UART0_485_TX; -#else - UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); -#endif -} +/* + * Callbacks + */ static void uart0_init(UNUSED(struct SerialHardware *, _hw), UNUSED(struct Serial *, ser)) { -#if defined(ARCH_BOARD_KS) && (ARCH & ARCH_BOARD_KS) - /* Set TX port as input with pull-up enabled to avoid - noise on the remote RX when TX is disabled. */ - cpuflags_t flags; - DISABLE_IRQSAVE(flags); - DDRE &= ~BV(PORTE1); - PORTE |= BV(PORTE1); - ENABLE_IRQRESTORE(flags); -#endif /* ARCH_BOARD_KS */ - -#if CONFIG_SER_TXFILL && (CONFIG_KBUS_PORT == 0) - /*! - * Set multiprocessor mode and 9 bit data frame. - * The receiver keep MPCM bit always on. When useful data - * is trasmitted the ninth bit is set and the receiver receive - * the frame. - * When useless fill bytes are sent the ninth bit is cleared - * and the receiver will ignore them. - */ - UCSR0A = BV(MPCM); - UCSR0B = BV(RXCIE) | BV(RXEN) | BV(UCSZ2); -#else - UCSR0B = BV(RXCIE) | BV(RXEN); -#endif - - SER_UART0_485_INIT; + SER_UART0_BUS_TXINIT; RTS_ON; } @@ -214,6 +337,23 @@ static void uart0_cleanup(UNUSED(struct SerialHardware *, _hw)) UCSR0B = 0; } +static void uart0_enabletxirq(struct SerialHardware *_hw) +{ + struct AvrSerial *hw = (struct AvrSerial *)_hw; + + /* + * WARNING: racy code here! The tx interrupt + * sets hw->sending to false when it runs with + * an empty fifo. The order of the statements + * in the if-block matters. + */ + if (!hw->sending) + { + hw->sending = true; + SER_UART0_BUS_TXBEGIN; + } +} + static void uart0_setbaudrate(UNUSED(struct SerialHardware *, _hw), unsigned long rate) { /* Compute baud-rate period */ @@ -224,7 +364,7 @@ static void uart0_setbaudrate(UNUSED(struct SerialHardware *, _hw), unsigned lon #endif UBRR0L = (period); - DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);) + //DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);) } static void uart0_setparity(UNUSED(struct SerialHardware *, _hw), int parity) @@ -236,38 +376,11 @@ static void uart0_setparity(UNUSED(struct SerialHardware *, _hw), int parity) #if AVR_HAS_UART1 -static void uart1_enabletxirq(UNUSED(struct SerialHardware *, _hw)) -{ -#if CONFIG_SER_TXFILL && (CONFIG_KBUS_PORT == 1) - UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN) | BV(UCSZ2); -#elif defined(SER_UART1_485_TX) - /* Disable receiver, enable transmitter, switch 485 transceiver. */ - UCSR1B = BV(UDRIE) | BV(TXEN); - SER_UART1_485_TX; -#else - UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); -#endif -} - static void uart1_init(UNUSED(struct SerialHardware *, _hw), UNUSED(struct Serial *, ser)) { - /* Set TX port as input with pull-up enabled to avoid - * noise on the remote RX when TX is disabled */ - cpuflags_t flags; - DISABLE_IRQSAVE(flags); - DDRD &= ~BV(PORTD3); - PORTD |= BV(PORTD3); - ENABLE_IRQRESTORE(flags); - -#if CONFIG_SER_TXFILL && (CONFIG_KBUS_PORT == 1) - /*! See comment in uart0_init() */ - UCSR1A = BV(MPCM); - UCSR1B = BV(RXCIE) | BV(RXEN) | BV(UCSZ2); -#else - UCSR1B = BV(RXCIE) | BV(RXEN); -#endif - SER_UART1_485_INIT; + SER_UART1_BUS_TXINIT; RTS_ON; + SER_STROBE_INIT; } static void uart1_cleanup(UNUSED(struct SerialHardware *, _hw)) @@ -275,6 +388,23 @@ static void uart1_cleanup(UNUSED(struct SerialHardware *, _hw)) UCSR1B = 0; } +static void uart1_enabletxirq(struct SerialHardware *_hw) +{ + struct AvrSerial *hw = (struct AvrSerial *)_hw; + + /* + * WARNING: racy code here! The tx interrupt + * sets hw->sending to false when it runs with + * an empty fifo. The order of the statements + * in the if-block matters. + */ + if (!hw->sending) + { + hw->sending = true; + SER_UART1_BUS_TXBEGIN; + } +} + static void uart1_setbaudrate(UNUSED(struct SerialHardware *, _hw), unsigned long rate) { /* Compute baud-rate period */ @@ -283,7 +413,7 @@ static void uart1_setbaudrate(UNUSED(struct SerialHardware *, _hw), unsigned lon UBRR1H = (period) >> 8; UBRR1L = (period); - DB(kprintf("uart1_setbaudrate(rate=%ld): period=%d\n", rate, period);) + //DB(kprintf("uart1_setbaudrate(rate=%ld): period=%d\n", rate, period);) } static void uart1_setparity(UNUSED(struct SerialHardware *, _hw), int parity) @@ -293,7 +423,6 @@ static void uart1_setparity(UNUSED(struct SerialHardware *, _hw), int parity) #endif // AVR_HAS_UART1 - static void spi_init(UNUSED(struct SerialHardware *, _hw), UNUSED(struct Serial *, ser)) { /* @@ -322,6 +451,23 @@ static void spi_cleanup(UNUSED(struct SerialHardware *, _hw)) SPI_DDR &= ~(BV(SPI_MISO_BIT) | BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT)); } +static void spi_starttx(struct SerialHardware *_hw) +{ + struct AvrSerial *hw = (struct AvrSerial *)_hw; + + cpuflags_t flags; + DISABLE_IRQSAVE(flags); + + /* Send data only if the SPI is not already transmitting */ + if (!hw->sending && !fifo_isempty(&ser_spi->txfifo)) + { + hw->sending = true; + SPDR = fifo_pop(&ser_spi->txfifo); + } + + ENABLE_IRQRESTORE(flags); +} + static void spi_setbaudrate(UNUSED(struct SerialHardware *, _hw), UNUSED(unsigned long, rate)) { // nop @@ -333,6 +479,87 @@ static void spi_setparity(UNUSED(struct SerialHardware *, _hw), UNUSED(int, pari } + +/* + * High-level interface data structures + */ +static const struct SerialHardwareVT UART0_VT = +{ + .init = uart0_init, + .cleanup = uart0_cleanup, + .setbaudrate = uart0_setbaudrate, + .setparity = uart0_setparity, + .enabletxirq = uart0_enabletxirq, +}; + +#if AVR_HAS_UART1 +static const struct SerialHardwareVT UART1_VT = +{ + .init = uart1_init, + .cleanup = uart1_cleanup, + .setbaudrate = uart1_setbaudrate, + .setparity = uart1_setparity, + .enabletxirq = uart1_enabletxirq, +}; +#endif // AVR_HAS_UART1 + +static const struct SerialHardwareVT SPI_VT = +{ + .init = spi_init, + .cleanup = spi_cleanup, + .setbaudrate = spi_setbaudrate, + .setparity = spi_setparity, + .enabletxirq = spi_starttx, +}; + +static struct AvrSerial UARTDescs[SER_CNT] = +{ + { + .hw = { + .table = &UART0_VT, + .txbuffer = uart0_txbuffer, + .rxbuffer = uart0_rxbuffer, + .txbuffer_size = CONFIG_UART0_TXBUFSIZE, + .rxbuffer_size = CONFIG_UART0_RXBUFSIZE, + }, + .sending = false, + }, +#if AVR_HAS_UART1 + { + .hw = { + .table = &UART1_VT, + .txbuffer = uart1_txbuffer, + .rxbuffer = uart1_rxbuffer, + .txbuffer_size = CONFIG_UART1_TXBUFSIZE, + .rxbuffer_size = CONFIG_UART1_RXBUFSIZE, + }, + .sending = false, + }, +#endif + { + .hw = { + .table = &SPI_VT, + .txbuffer = spi_txbuffer, + .rxbuffer = spi_rxbuffer, + .txbuffer_size = CONFIG_SPI_TXBUFSIZE, + .rxbuffer_size = CONFIG_SPI_RXBUFSIZE, + }, + .sending = false, + } +}; + +struct SerialHardware* ser_hw_getdesc(int unit) +{ + ASSERT(unit < SER_CNT); + return &UARTDescs[unit].hw; +} + + + +/* + * Interrupt handlers + */ + #if CONFIG_SER_HWHANDSHAKE //! This interrupt is triggered when the CTS line goes high @@ -351,50 +578,37 @@ SIGNAL(SIG_CTS) */ SIGNAL(SIG_UART0_DATA) { + SER_STROBE_ON; + struct FIFOBuffer * const txfifo = &ser_uart0->txfifo; if (fifo_isempty(txfifo)) { -#if CONFIG_SER_TXFILL && (CONFIG_KBUS_PORT == 0) - /* - * To avoid audio interference: always transmit useless char. - * Send the byte with the ninth bit cleared, the receiver in MCPM mode - * will ignore it. - */ - UCSR0B &= ~BV(TXB8); - UDR0 = SER_FILL_BYTE; -#elif defined(SER_UART0_485_RX) - /* - * - Disable UDR empty interrupt - * - Disable the transmitter (the in-progress transfer will complete) - * - Enable the transmit complete interrupt for the 485 tranceiver. - */ - UCSR0B = BV(TXCIE); -#else - /* Disable UDR empty interrupt and transmitter */ - UCSR0B = BV(RXCIE) | BV(RXEN); + SER_UART0_BUS_TXEND; +#ifndef SER_UART0_BUS_TXOFF + UARTDescs[SER_UART0].sending = false; #endif } -#if CONFIG_SER_HWHANDSHAKE +#if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103 else if (!IS_CTS_ON) { // Disable rx interrupt and tx, enable CTS interrupt - UCSR0B = BV(RXCIE) | BV(RXEN); + // UNTESTED + UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN); sbi(EIFR, EIMSKB_CTS); sbi(EIMSK, EIMSKB_CTS); } -#endif // CONFIG_SER_HWHANDSHAKE +#endif else { -#if CONFIG_SER_TXFILL && (CONFIG_KBUS_PORT == 0) - /* Send with ninth bit set. Receiver in MCPM mode will receive it */ - UCSR0B |= BV(TXB8); -#endif - UDR0 = fifo_pop(txfifo); + char c = fifo_pop(txfifo); + SER_UART0_BUS_TXCHAR(c); } + + SER_STROBE_OFF; } -#ifdef SER_UART0_485_RX +#ifdef SER_UART0_BUS_TXOFF /*! * Serial port 0 TX complete interrupt handler. * @@ -403,16 +617,29 @@ SIGNAL(SIG_UART0_DATA) * We need to wait until the last character has been * transmitted before switching the 485 transceiver to * receive mode. + * + * The txfifo might have been refilled by putchar() while + * we were waiting for the transmission complete interrupt. + * In this case, we must restart the UDR empty interrupt, + * otherwise we'd stop the serial port with some data + * still pending in the buffer. */ SIGNAL(SIG_UART0_TRANS) { - /* Turn the 485 tranceiver into receive mode. */ - SER_UART0_485_RX; + SER_STROBE_ON; + + struct FIFOBuffer * const txfifo = &ser_uart0->txfifo; + if (fifo_isempty(txfifo)) + { + SER_UART0_BUS_TXOFF; + UARTDescs[SER_UART0].sending = false; + } + else + UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); - /* Enable UART receiver and receive interrupt. */ - UCSR0B = BV(RXCIE) | BV(RXEN); + SER_STROBE_OFF; } -#endif /* SER_UART0_485_RX */ +#endif /* SER_UART0_BUS_TXOFF */ #if AVR_HAS_UART1 @@ -422,50 +649,37 @@ SIGNAL(SIG_UART0_TRANS) */ SIGNAL(SIG_UART1_DATA) { + SER_STROBE_ON; + struct FIFOBuffer * const txfifo = &ser_uart1->txfifo; if (fifo_isempty(txfifo)) { -#if CONFIG_SER_TXFILL && (CONFIG_KBUS_PORT == 1) - /* - * To avoid audio interference: always transmit useless char. - * Send the byte with the ninth bit cleared, the receiver in MCPM mode - * will ignore it. - */ - UCSR1B &= ~BV(TXB8); - UDR1 = SER_FILL_BYTE; -#elif defined(SER_UART1_485_RX) - /* - * - Disable UDR empty interrupt - * - Disable the transmitter (the in-progress transfer will complete) - * - Enable the transmit complete interrupt for the 485 tranceiver. - */ - UCSR1B = BV(TXCIE); -#else - /* Disable UDR empty interrupt and transmitter */ - UCSR1B = BV(RXCIE) | BV(RXEN); + SER_UART1_BUS_TXEND; +#ifndef SER_UART1_BUS_TXOFF + UARTDescs[SER_UART1].sending = false; #endif } -#if CONFIG_SER_HWHANDSHAKE - else if (IS_CTS_OFF) +#if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103 + else if (!IS_CTS_ON) { // Disable rx interrupt and tx, enable CTS interrupt - UCSR1B = BV(RXCIE) | BV(RXEN); + // UNTESTED + UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); sbi(EIFR, EIMSKB_CTS); sbi(EIMSK, EIMSKB_CTS); } -#endif // CONFIG_SER_HWHANDSHAKE +#endif else { -#if CONFIG_SER_TXFILL && (CONFIG_KBUS_PORT == 1) - /* Send with ninth bit set. Receiver in MCPM mode will receive it */ - UCSR1B |= BV(TXB8); -#endif - UDR1 = fifo_pop(txfifo); + char c = fifo_pop(txfifo); + SER_UART1_BUS_TXCHAR(c); } + + SER_STROBE_OFF; } -#ifdef SER_UART1_485_RX +#ifdef SER_UART1_BUS_TXOFF /*! * Serial port 1 TX complete interrupt handler. * @@ -473,13 +687,20 @@ SIGNAL(SIG_UART1_DATA) */ SIGNAL(SIG_UART1_TRANS) { - /* Turn the 485 tranceiver into receive mode. */ - SER_UART1_485_RX; + SER_STROBE_ON; + + struct FIFOBuffer * const txfifo = &ser_uart1->txfifo; + if (fifo_isempty(txfifo)) + { + SER_UART1_BUS_TXOFF; + UARTDescs[SER_UART1].sending = false; + } + else + UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); - /* Enable UART receiver and receive interrupt. */ - UCSR1B = BV(RXCIE) | BV(RXEN); + SER_STROBE_OFF; } -#endif /* SER_UART1_485_RX */ +#endif /* SER_UART1_BUS_TXOFF */ #endif // AVR_HAS_UART1 @@ -492,12 +713,20 @@ SIGNAL(SIG_UART1_TRANS) * disabled. Using INTERRUPT() is troublesome when the serial * is heavily loaded, because an interrupt could be retriggered * when executing the handler prologue before RXCIE is disabled. + * + * \note The code that re-enables interrupts is commented out + * because in some nasty cases the interrupt is retriggered. + * This is probably due to the RXC flag being set before + * RXCIE is cleared. Unfortunately the RXC flag is read-only + * and can't be cleared by code. */ SIGNAL(SIG_UART0_RECV) { + SER_STROBE_ON; + /* Disable Recv complete IRQ */ - UCSR0B &= ~BV(RXCIE); - ENABLE_INTS; + //UCSR0B &= ~BV(RXCIE); + //ENABLE_INTS; /* Should be read before UDR */ ser_uart0->status |= UCSR0A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR); @@ -521,7 +750,10 @@ SIGNAL(SIG_UART0_RECV) } /* Reenable receive complete int */ - UCSR0B |= BV(RXCIE); + //DISABLE_INTS; + //UCSR0B |= BV(RXCIE); + + SER_STROBE_OFF; } @@ -535,12 +767,16 @@ SIGNAL(SIG_UART0_RECV) * disabled. Using INTERRUPT() is troublesome when the serial * is heavily loaded, because an interrupt could be retriggered * when executing the handler prologue before RXCIE is disabled. + * + * \see SIGNAL(SIG_UART0_RECV) */ SIGNAL(SIG_UART1_RECV) { + SER_STROBE_ON; + /* Disable Recv complete IRQ */ - UCSR1B &= ~BV(RXCIE); - ENABLE_INTS; + //UCSR1B &= ~BV(RXCIE); + //ENABLE_INTS; /* Should be read before UDR */ ser_uart1->status |= UCSR1A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR); @@ -550,8 +786,9 @@ SIGNAL(SIG_UART1_RECV) */ char c = UDR1; struct FIFOBuffer * const rxfifo = &ser_uart1->rxfifo; + //ASSERT_VALID_FIFO(rxfifo); - if (fifo_isfull(rxfifo)) + if (UNLIKELY(fifo_isfull(rxfifo))) ser_uart1->status |= SERRF_RXFIFOOVERRUN; else { @@ -561,40 +798,15 @@ SIGNAL(SIG_UART1_RECV) RTS_OFF; #endif } - /* Reenable receive complete int */ - UCSR1B |= BV(RXCIE); + /* Re-enable receive complete int */ + //UCSR1B |= BV(RXCIE); + + SER_STROBE_OFF; } #endif // AVR_HAS_UART1 -/* - * SPI Flag: true if we are transmitting/receiving with the SPI. - * - * This kludge is necessary because the SPI sends and receives bytes - * at the same time and the SPI IRQ is unique for send/receive. - * The only way to start transmission is to write data in SPDR (this - * is done by spi_starttx()). We do this *only* if a transfer is - * not already started. - */ -static volatile bool spi_sending = false; - -static void spi_starttx(UNUSED(struct SerialHardware *, ctx)) -{ - cpuflags_t flags; - - DISABLE_IRQSAVE(flags); - - /* Send data only if the SPI is not already transmitting */ - if (!spi_sending && !fifo_isempty(&ser_spi->txfifo)) - { - SPDR = fifo_pop(&ser_spi->txfifo); - spi_sending = true; - } - - ENABLE_IRQRESTORE(flags); -} - /*! * SPI interrupt handler */ @@ -613,50 +825,5 @@ SIGNAL(SIG_SPI) if (!fifo_isempty(&ser_spi->txfifo)) SPDR = fifo_pop(&ser_spi->txfifo); else - spi_sending = false; -} - - -static const struct SerialHardwareVT UART0_VT = -{ - .init = uart0_init, - .cleanup = uart0_cleanup, - .setbaudrate = uart0_setbaudrate, - .setparity = uart0_setparity, - .enabletxirq = uart0_enabletxirq, -}; - -#if AVR_HAS_UART1 -static const struct SerialHardwareVT UART1_VT = -{ - .init = uart1_init, - .cleanup = uart1_cleanup, - .setbaudrate = uart1_setbaudrate, - .setparity = uart1_setparity, - .enabletxirq = uart1_enabletxirq, -}; -#endif // AVR_HAS_UART1 - -static const struct SerialHardwareVT SPI_VT = -{ - .init = spi_init, - .cleanup = spi_cleanup, - .setbaudrate = spi_setbaudrate, - .setparity = spi_setparity, - .enabletxirq = spi_starttx, -}; - -static struct SerialHardware UARTDescs[SER_CNT] = -{ - { .table = &UART0_VT }, -#if AVR_HAS_UART1 - { .table = &UART1_VT }, -#endif - { .table = &SPI_VT }, -}; - -struct SerialHardware* ser_hw_getdesc(int unit) -{ - ASSERT(unit < SER_CNT); - return &UARTDescs[unit]; + UARTDescs[SER_SPI].sending = false; }