X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=drv%2Fser_dsp56k.c;h=efdb2e2bcc0a899526736d6782266fde753f02d6;hb=0c26c885fbf3ab9b731e4733eff7713d3980b1ea;hp=a5a96fb7fb404bd106d1f5fdfbde32e34e9cec77;hpb=277b540c0764dd376dcf583acdc97a2b2fd3d8e6;p=bertos.git diff --git a/drv/ser_dsp56k.c b/drv/ser_dsp56k.c index a5a96fb7..efdb2e2b 100755 --- a/drv/ser_dsp56k.c +++ b/drv/ser_dsp56k.c @@ -1,7 +1,7 @@ /*! * \file * * @@ -15,6 +15,9 @@ /*#* *#* $Log$ + *#* Revision 1.7 2004/10/19 08:57:15 bernie + *#* Bugfixes for DSP56K serial driver from scfirm. + *#* *#* Revision 1.5 2004/08/25 14:12:08 rasky *#* Aggiornato il comment block dei log RCS *#* @@ -26,15 +29,14 @@ *#* *#* Revision 1.2 2004/05/23 18:21:53 bernie *#* Trim CVS logs and cleanup header info. - *#* *#*/ #include "ser.h" #include "ser_p.h" -#include #include +#include #include -#include +#include // GPIO E is shared with SPI (in DSP56807). Pins 0&1 are TXD0 and RXD0. To use // the serial, we need to disable the GPIO functions on them. @@ -49,6 +51,11 @@ #error error flags do not match with register bits #endif +static unsigned char ser0_fifo_rx[CONFIG_SER0_FIFOSIZE_RX]; +static unsigned char ser0_fifo_tx[CONFIG_SER0_FIFOSIZE_TX]; +static unsigned char ser1_fifo_rx[CONFIG_SER1_FIFOSIZE_RX]; +static unsigned char ser1_fifo_tx[CONFIG_SER1_FIFOSIZE_TX]; + struct SCI { struct SerialHardware hw; @@ -65,7 +72,7 @@ static inline void enable_tx_irq_bare(volatile struct REG_SCI_STRUCT* regs) static inline void enable_rx_irq_bare(volatile struct REG_SCI_STRUCT* regs) { - regs->CR |= REG_SCI_CR_RIE | REG_SCI_CR_REIE; + regs->CR |= REG_SCI_CR_RIE; } static inline void disable_tx_irq_bare(volatile struct REG_SCI_STRUCT* regs) @@ -122,18 +129,29 @@ static void rx_isr(const struct SCI *hw) #pragma interrupt warn volatile struct REG_SCI_STRUCT* regs = hw->regs; + // Propagate errors hw->serial->status |= regs->SR & (SERRF_PARITYERROR | SERRF_RXSROVERRUN | SERRF_FRAMEERROR | SERRF_NOISEERROR); + /* + * Serial IRQ can happen for two reason: data ready (RDRF) or overrun (OR) + * If the data is ready, we need to fetch it from the data register or + * the interrupt will retrigger immediatly. In case of overrun, instead, + * the value of the data register is meaningless. + */ + if (regs->SR & REG_SCI_SR_RDRF) + { + unsigned char data = regs->DR; + + if (fifo_isfull(&hw->serial->rxfifo)) if (fifo_isfull(&hw->serial->rxfifo)) hw->serial->status |= SERRF_RXFIFOOVERRUN; else fifo_push(&hw->serial->rxfifo, regs->DR); - // Writing anything to the status register clear the - // error bits. + // Writing anything to the status register clear the error bits. regs->SR = 0; } @@ -200,14 +218,28 @@ static const struct SerialHardwareVT SCI_VT = static struct SCI SCIDescs[2] = { { - .hw = { .table = &SCI_VT }, + .hw = + { + .table = &SCI_VT, + .rxbuffer = ser0_fifo_rx, + .txbuffer = ser0_fifo_tx, + .rxbuffer_size = countof(ser0_fifo_rx), + .txbuffer_size = countof(ser0_fifo_tx), + }, .regs = ®_SCI[0], .irq_rx = IRQ_SCI0_RECEIVER_FULL, .irq_tx = IRQ_SCI0_TRANSMITTER_READY, }, { - .hw = { .table = &SCI_VT }, + .hw = + { + .table = &SCI_VT, + .rxbuffer = ser1_fifo_rx, + .txbuffer = ser1_fifo_tx, + .rxbuffer_size = countof(ser1_fifo_rx), + .txbuffer_size = countof(ser1_fifo_tx), + }, .regs = ®_SCI[1], .irq_rx = IRQ_SCI1_RECEIVER_FULL, .irq_tx = IRQ_SCI1_TRANSMITTER_READY,