X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=examples%2Fat91sam7%2Fcfg%2Fcfg_ser.h;fp=examples%2Fat91sam7%2Fcfg%2Fcfg_ser.h;h=27b14c3efa23adeb2aa5ae0256082fd36e18a60d;hb=d43c956fc9313bda9ddbd2cc66d910e22dc7a9c5;hp=0000000000000000000000000000000000000000;hpb=c9d1a7e9cc28f4d94fff284a4ca09a23f8eea855;p=bertos.git diff --git a/examples/at91sam7/cfg/cfg_ser.h b/examples/at91sam7/cfg/cfg_ser.h new file mode 100644 index 00000000..27b14c3e --- /dev/null +++ b/examples/at91sam7/cfg/cfg_ser.h @@ -0,0 +1,107 @@ +/** + * \file + * + * + * \brief Configuration file for serial module. + * + * \version $Id$ + * + * \author Daniele Basile + */ + +#ifndef CFG_SER_H +#define CFG_SER_H + +/** + * Example of setting for serial port and + * spi port. + * Edit these define for your project. + */ + +/// [bytes] Size of the outbound FIFO buffer for port 0. +#define CONFIG_UART0_TXBUFSIZE 32 + +/// [bytes] Size of the inbound FIFO buffer for port 0. +#define CONFIG_UART0_RXBUFSIZE 32 + +/// [bytes] Size of the outbound FIFO buffer for port 1. +#define CONFIG_UART1_TXBUFSIZE 32 + +/// [bytes] Size of the inbound FIFO buffer for port 1. +#define CONFIG_UART1_RXBUFSIZE 32 + + +/// [bytes] Size of the outbound FIFO buffer for SPI port (AVR only) +#define CONFIG_SPI_TXBUFSIZE 32 + +/// [bytes] Size of the inbound FIFO buffer for SPI port (AVR only) +#define CONFIG_SPI_RXBUFSIZE 32 + +/// [bytes] Size of the outbound FIFO buffer for SPI port 0. +#define CONFIG_SPI0_TXBUFSIZE 32 + +/// [bytes] Size of the inbound FIFO buffer for SPI port 0. +#define CONFIG_SPI0_RXBUFSIZE 32 + +/// [bytes] Size of the outbound FIFO buffer for SPI port 1. +#define CONFIG_SPI1_TXBUFSIZE 32 + +/// [bytes] Size of the inbound FIFO buffer for SPI port 1. +#define CONFIG_SPI1_RXBUFSIZE 32 + +/// SPI data order (AVR only). +#define CONFIG_SPI_DATA_ORDER SER_MSB_FIRST + +/// SPI clock division factor (AVR only). +#define CONFIG_SPI_CLOCK_DIV 16 + +/// SPI clock polarity: 0 = normal low, 1 = normal high (AVR only). +#define CONFIG_SPI_CLOCK_POL 0 + +/// SPI clock phase: 0 = sample on first edge, 1 = sample on second clock edge (AVR only). +#define CONFIG_SPI_CLOCK_PHASE 0 + +/// Default transmit timeout (ms). Set to -1 to disable timeout support. +#define CONFIG_SER_TXTIMEOUT -1 + +/// Default receive timeout (ms). Set to -1 to disable timeout support. +#define CONFIG_SER_RXTIMEOUT -1 + +/// Use RTS/CTS handshake +#define CONFIG_SER_HWHANDSHAKE 0 + +/// Default baud rate (set to 0 to disable). +#define CONFIG_SER_DEFBAUDRATE 0 + +/// For serial debug. +#define CONFIG_SER_STROBE 0 + +#endif /* CFG_SER_H */