X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=examples%2Ftriface%2Fhw%2Fhw_sipo.h;h=87e5736a642d053c7bca384108dca06f9b3a27b9;hb=1eecdfdefd523e5d412f5569f99a37cd2760ed0f;hp=f31497f27543a68448cf41f95e0d72f44689a5ae;hpb=ee3a4e534d8c013ef12d932e5325f62d128d00d8;p=bertos.git

diff --git a/examples/triface/hw/hw_sipo.h b/examples/triface/hw/hw_sipo.h
index f31497f2..87e5736a 100644
--- a/examples/triface/hw/hw_sipo.h
+++ b/examples/triface/hw/hw_sipo.h
@@ -47,6 +47,19 @@
 
 #include <avr/io.h>
 
+/**
+ * Mapping sipo connection on board.
+ * See schematics for more info.
+ */
+typedef enum SipoMap
+{
+	TRIFACE_DOUT = 0,
+
+	SIPO_CNT
+} SipoMap;
+
+
+
 //Set output pin for sipo
 #define SCK_OUT            (DDRB |= BV(PB1))  // Shift register clock input pin
 #define SOUT_OUT           (DDRB |= BV(PB2))  // Serial data input pin
@@ -73,8 +86,9 @@
  * Drive pin to load the bit, presented in serial-in pin,
  * into sipo shift register.
  */
-#define SIPO_SI_CLOCK() \
+#define SIPO_SI_CLOCK(clk_pol) \
 	do{ \
+		(void)clk_pol; \
 		SCK_HIGH; \
 		SCK_LOW; \
 	}while(0)
@@ -82,8 +96,10 @@
 /**
  * Clock the content of shift register to output.
  */
-#define SIPO_LOAD() \
+#define SIPO_LOAD(device, load_pol) \
 	do { \
+		(void)device; \
+		(void)load_pol; \
 		SLOAD_OUT_HIGH; \
 		SLOAD_OUT_LOW; \
 	}while(0)
@@ -93,6 +109,31 @@
  */
 #define SIPO_ENABLE() OE_LOW;
 
+/**
+ * Set logic level for load signal
+ */
+#define SIPO_SET_LD_LEVEL(device, load_pol) \
+	do { \
+		(void)device; \
+		if(load_pol) \
+			SLOAD_OUT_HIGH; \
+		else \
+			SLOAD_OUT_LOW; \
+	} while (0)
+
+
+/**
+ * Sel logic level for clock signal
+ */
+#define SIPO_SET_CLK_LEVEL(clock_pol) \
+	do { \
+		if(clock_pol) \
+			SCK_HIGH; \
+		else \
+			SCK_LOW; \
+	} while (0)
+
+#define SIPO_SET_SI_LEVEL()     SIPO_SI_LOW()
 
 /**
  * Do everything needed in order to init the SIPO pins.