X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=examples%2Ftriface%2Fhw%2Fhw_sipo.h;h=87e5736a642d053c7bca384108dca06f9b3a27b9;hb=9a9d8e33e942f8a2af0828181203c4a1def62adb;hp=f41e35f95889903874a529fea847f5179c0bb78d;hpb=24c21c92d29b76a3f0de0a107f4bafef7bb0f812;p=bertos.git

diff --git a/examples/triface/hw/hw_sipo.h b/examples/triface/hw/hw_sipo.h
index f41e35f9..87e5736a 100644
--- a/examples/triface/hw/hw_sipo.h
+++ b/examples/triface/hw/hw_sipo.h
@@ -26,7 +26,7 @@
  * invalidate any other reasons why the executable file might be covered by
  * the GNU General Public License.
  *
- * Copyright 2003, 2004, 2006 Develer S.r.l. (http://www.develer.com/)
+ * Copyright 2003, 2004, 2006, 2009 Develer S.r.l. (http://www.develer.com/)
  * Copyright 2000 Bernie Innocenti <bernie@codewiz.org>
  *
  * -->
@@ -37,23 +37,115 @@
  * \version $Id$
  *
  * \author Andrea Grandi <andrea@develer.com>
+ * \author Daniele Basile <asterix@develer.com>
  */
+
 #ifndef HW_SIPO_H
 #define HW_SIPO_H
 
-#define LOAD_HIGH     (PORTB |= BV(PB3))
-#define LOAD_LOW      (PORTB &= ~BV(PB3))
-#define LOAD_INIT     (DDRB |= BV(PB3))
-#define SET_SCK_OUT   (DDRB |= BV(PB1))
-#define SET_SOUT_OUT  (DDRB |= BV(PB2))
-#define CLOCK_HIGH    (PORTB |= BV(PB1))
-#define CLOCK_LOW     (PORTB &= ~BV(PB1))
-#define SET_SOUT_HIGH (PORTB |= BV(PB2))
-#define SET_SOUT_LOW  (PORTB &= ~BV(PB2))
-#define CLOCK_PULSE   do { CLOCK_HIGH; CLOCK_LOW; } while(0)
+#include <cfg/macros.h>
+
+#include <avr/io.h>
+
+/**
+ * Mapping sipo connection on board.
+ * See schematics for more info.
+ */
+typedef enum SipoMap
+{
+	TRIFACE_DOUT = 0,
+
+	SIPO_CNT
+} SipoMap;
+
+
+
+//Set output pin for sipo
+#define SCK_OUT            (DDRB |= BV(PB1))  // Shift register clock input pin
+#define SOUT_OUT           (DDRB |= BV(PB2))  // Serial data input pin
+#define SLOAD_OUT          (DDRB |= BV(PB3))  // Storage register clock input pin
+#define OE_OUT             (DDRG |= BV(PG3))  // Output enable pin
+
+//Define output level
+#define SCK_HIGH           (PORTB |= BV(PB1))
+#define SCK_LOW            (PORTB &= ~BV(PB1))
+#define SOUT_OUT_HIGH      (PORTB |= BV(PB2))
+#define SOUT_OUT_LOW       (PORTB &= ~BV(PB2))
+#define SLOAD_OUT_HIGH     (PORTB |= BV(PB3))
+#define SLOAD_OUT_LOW      (PORTB &= ~BV(PB3))
+#define OE_LOW             (PORTG &= BV(PG3))
+
+/**
+ * Define the macros needed to set the serial input bit of SIPO device
+ * low or high.
+ */
+#define SIPO_SI_HIGH()    SOUT_OUT_HIGH
+#define SIPO_SI_LOW()     SOUT_OUT_LOW
+
+/**
+ * Drive pin to load the bit, presented in serial-in pin,
+ * into sipo shift register.
+ */
+#define SIPO_SI_CLOCK(clk_pol) \
+	do{ \
+		(void)clk_pol; \
+		SCK_HIGH; \
+		SCK_LOW; \
+	}while(0)
+
+/**
+ * Clock the content of shift register to output.
+ */
+#define SIPO_LOAD(device, load_pol) \
+	do { \
+		(void)device; \
+		(void)load_pol; \
+		SLOAD_OUT_HIGH; \
+		SLOAD_OUT_LOW; \
+	}while(0)
+
+/**
+ * Enable the shift register output.
+ */
+#define SIPO_ENABLE() OE_LOW;
+
+/**
+ * Set logic level for load signal
+ */
+#define SIPO_SET_LD_LEVEL(device, load_pol) \
+	do { \
+		(void)device; \
+		if(load_pol) \
+			SLOAD_OUT_HIGH; \
+		else \
+			SLOAD_OUT_LOW; \
+	} while (0)
+
+
+/**
+ * Sel logic level for clock signal
+ */
+#define SIPO_SET_CLK_LEVEL(clock_pol) \
+	do { \
+		if(clock_pol) \
+			SCK_HIGH; \
+		else \
+			SCK_LOW; \
+	} while (0)
+
+#define SIPO_SET_SI_LEVEL()     SIPO_SI_LOW()
 
-#define OE_OUT        (DDRG |= BV(PG3))
-#define OE_LOW        (PORTG &= BV(PG3))
+/**
+ * Do everything needed in order to init the SIPO pins.
+ */
+#define SIPO_INIT_PIN() \
+	do { \
+		OE_OUT; \
+		SOUT_OUT; \
+		SCK_OUT; \
+		SLOAD_OUT; \
+		SIPO_ENABLE(); \
+	} while(0)
 
 
-#endif // HW_SIPO_H
+#endif /* HW_SIPO_H */