X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=rmslog%2Fcfg%2Fcfg_ser.h;h=b2524ccbeb1818fe0bbee76935216b20f6d70f57;hb=953c42c0ea7e1c27793ba465db862e2fbc7ffdf9;hp=91a10e0b2d8ade049eeb03b95150797d6728a29f;hpb=d628a65a3e1ab1a3e3f11dcbd65bca85174d36a9;p=rmslog.git

diff --git a/rmslog/cfg/cfg_ser.h b/rmslog/cfg/cfg_ser.h
index 91a10e0..b2524cc 100644
--- a/rmslog/cfg/cfg_ser.h
+++ b/rmslog/cfg/cfg_ser.h
@@ -49,63 +49,14 @@
  * $WIZ$ type = "int"
  * $WIZ$ min = 2
  */
-#define CONFIG_UART0_TXBUFSIZE  32
+#define CONFIG_UART0_TXBUFSIZE  16
 
 /**
  * Size of the inbound FIFO buffer for port 0 [bytes].
  * $WIZ$ type = "int"
  * $WIZ$ min = 2
  */
-#define CONFIG_UART0_RXBUFSIZE  32
-
-/**
- * Size of the outbound FIFO buffer for port 1 [bytes].
- * $WIZ$ type = "int"
- * $WIZ$ min = 2
- * $WIZ$ supports = "lm3s or lpc2 or (at91 and not atmega8 and not atmega168 and not atmega32)"
- */
-#define CONFIG_UART1_TXBUFSIZE  32
-
-/**
- * Size of the inbound FIFO buffer for port 1 [bytes].
- * $WIZ$ type = "int"
- * $WIZ$ min = 2
- * $WIZ$ supports = "lm3s or lpc2 or (at91 and not atmega8 and not atmega168 and not atmega32)"
- */
-#define CONFIG_UART1_RXBUFSIZE  32
-
-/**
- * Size of the outbound FIFO buffer for port 2 [bytes].
- * $WIZ$ type = "int"
- * $WIZ$ min = 2
- * $WIZ$ supports = "lm3s or lpc2"
- */
-#define CONFIG_UART2_TXBUFSIZE  32
-
-/**
- * Size of the inbound FIFO buffer for port 2 [bytes].
- * $WIZ$ type = "int"
- * $WIZ$ min = 2
- * $WIZ$ supports = "lm3s or lpc2"
- */
-#define CONFIG_UART2_RXBUFSIZE  32
-
-/**
- * Size of the outbound FIFO buffer for port 3 [bytes].
- * $WIZ$ type = "int"
- * $WIZ$ min = 2
- * $WIZ$ supports = "lpc2"
- */
-#define CONFIG_UART3_TXBUFSIZE  32
-
-/**
- * Size of the inbound FIFO buffer for port 3 [bytes].
- * $WIZ$ type = "int"
- * $WIZ$ min = 2
- * $WIZ$ supports = "lpc2"
- */
-#define CONFIG_UART3_RXBUFSIZE  32
-
+#define CONFIG_UART0_RXBUFSIZE  512
 
 /**
  * Size of the outbound FIFO buffer for SPI port [bytes].
@@ -113,7 +64,7 @@
  * $WIZ$ min = 2
  * $WIZ$ supports = "avr"
  */
-#define CONFIG_SPI_TXBUFSIZE    32
+#define CONFIG_SPI_TXBUFSIZE    0
 
 /**
  * Size of the inbound FIFO buffer for SPI port [bytes].
@@ -121,39 +72,7 @@
  * $WIZ$ min = 2
  * $WIZ$ supports = "avr"
  */
-#define CONFIG_SPI_RXBUFSIZE    32
-
-/**
- * Size of the outbound FIFO buffer for SPI port 0 [bytes].
- * $WIZ$ type = "int"
- * $WIZ$ min = 2
- * $WIZ$ supports = "at91"
- */
-#define CONFIG_SPI0_TXBUFSIZE	32
-
-/**
- * Size of the inbound FIFO buffer for SPI port 0 [bytes].
- * $WIZ$ type = "int"
- * $WIZ$ min = 2
- * $WIZ$ supports = "at91"
- */
-#define CONFIG_SPI0_RXBUFSIZE	32
-
-/**
- * Size of the outbound FIFO buffer for SPI port 1 [bytes].
- * $WIZ$ type = "int"
- * $WIZ$ min = 2
- * $WIZ$ supports = "at91"
- */
-#define CONFIG_SPI1_TXBUFSIZE	32
-
-/**
- * Size of the inbound FIFO buffer for SPI port 1 [bytes].
- * $WIZ$ type = "int"
- * $WIZ$ min = 2
- * $WIZ$ supports = "at91"
- */
-#define CONFIG_SPI1_RXBUFSIZE	32
+#define CONFIG_SPI_RXBUFSIZE    0
 
 /**
  * SPI data order.
@@ -169,7 +88,7 @@
  * $WIZ$ type = "int"
  * $WIZ$ supports = "avr"
  */
-#define CONFIG_SPI_CLOCK_DIV	16
+#define CONFIG_SPI_CLOCK_DIV	128
 
 /**
  * SPI clock polarity: normal low or normal high.
@@ -200,7 +119,7 @@
  * $WIZ$ type = "int"
  * $WIZ$ min = -1
  */
-#define CONFIG_SER_RXTIMEOUT    -1
+#define CONFIG_SER_RXTIMEOUT    200
 
 /**
  * Use RTS/CTS handshake.