lm3s1968: rename the function __delay() to lm3s_busyWait().

git-svn-id: https://src.develer.com/svnoss/bertos/trunk@3412 38d2e660-2303-0410-9eaa-f027e97ec537

diff --git a/bertos/cpu/cortex-m3/drv/clock_lm3s.c b/bertos/cpu/cortex-m3/drv/clock_lm3s.c
index 1bc63f7ac24fdda41125a8f300c6db4f55d51d06..76e901bda6430b3ca3597de4b2d816fd1258a733 100644 (file)
--- a/bertos/cpu/cortex-m3/drv/clock_lm3s.c
+++ b/bertos/cpu/cortex-m3/drv/clock_lm3s.c
@@ -51,7 +51,7 @@
 /*
  * Very small delay: each loop takes 3 cycles.
  */
-void NAKED __delay(unsigned long iterations)
+void NAKED lm3s_busyWait(unsigned long iterations)
 {
        register uint32_t __n asm("r0") = iterations;
 
@@ -113,7 +113,7 @@ void clock_set_rate(void)
        HWREG(SYSCTL_RCC) = rcc;
        HWREG(SYSCTL_RCC) = rcc2;
 
-       __delay(16);
+       lm3s_busyWait(16);
 
        /*
         * Step #2: select the crystal value (XTAL) and oscillator source
@@ -139,7 +139,7 @@ void clock_set_rate(void)
         HWREG(SYSCTL_RCC) = rcc;
        HWREG(SYSCTL_RCC) = rcc2;
 
-       __delay(16);
+       lm3s_busyWait(16);
 
        /*
         * Step #3: select the desired system divider (SYSDIV) in RCC/RCC2 and
@@ -171,5 +171,5 @@ void clock_set_rate(void)
 
        HWREG(SYSCTL_RCC) = rcc;
 
-       __delay(16);
+       lm3s_busyWait(16);
 }

diff --git a/bertos/cpu/cortex-m3/drv/clock_lm3s.h b/bertos/cpu/cortex-m3/drv/clock_lm3s.h
index 039401842f1b2cc5bbfccd98623e643f7ed7eef5..564afb17bc8812c4f67daa8e2f933a90bf8c7fb8 100644 (file)
--- a/bertos/cpu/cortex-m3/drv/clock_lm3s.h
+++ b/bertos/cpu/cortex-m3/drv/clock_lm3s.h
@@ -41,7 +41,7 @@
 /* Crystal frequency attached to the main oscillator. */
 #define XTAL_FREQ      SYSCTL_RCC_XTAL_8MHZ
 
-extern void __delay(unsigned long iterations);
+extern void lm3s_busyWait(unsigned long iterations);
 
 unsigned long clock_get_rate(void);
 void clock_set_rate(void);

diff --git a/bertos/cpu/cortex-m3/drv/kdebug_lm3s.c b/bertos/cpu/cortex-m3/drv/kdebug_lm3s.c
index e96c371f2c988c299aad551889067b023f7502c1..d7be790a0a59090dcb2205b82774ab5b92e767e2 100644 (file)
--- a/bertos/cpu/cortex-m3/drv/kdebug_lm3s.c
+++ b/bertos/cpu/cortex-m3/drv/kdebug_lm3s.c
@@ -37,7 +37,7 @@
 
 #include <cfg/cfg_debug.h>
 #include <cfg/macros.h> /* for BV() */
-#include <drv/clock_lm3s.h> /* __delay() */
+#include <drv/clock_lm3s.h> /* lm3s_busyWait() */
 #include <drv/gpio_lm3s.h>
 #include <io/lm3s.h>
 #include "kdebug_lm3s.h"
@@ -125,7 +125,8 @@ INLINE void kdbg_hw_init(void)
        /* Enable the peripheral clock */
        SYSCTL_RCGC1_R |= SYSCTL_RCGC1_UART0;
        SYSCTL_RCGC2_R |= SYSCTL_RCGC2_GPIOA;
-       __delay(512);
+       lm3s_busyWait(512);
+
        /* Set GPIO A0 and A1 as UART pins */
        lm3s_gpio_pin_config(GPIO_PORTA_BASE, BV(0) | BV(1),
                        GPIO_DIR_MODE_HW, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);

diff --git a/examples/lm3s1968/hw/hw_lcd.h b/examples/lm3s1968/hw/hw_lcd.h
index c59dcb77bf45110b4a175d615e88bd05b870a667..dd2d88d79d6bb45ec8a01ff4e3f7801f6d54b67b 100644 (file)
--- a/examples/lm3s1968/hw/hw_lcd.h
+++ b/examples/lm3s1968/hw/hw_lcd.h
@@ -97,7 +97,7 @@ INLINE void lcd_bus_init(void)
        SYSCTL_RCGC1_R |= SYSCTL_RCGC1_SSI0;
        SYSCTL_RCGC2_R |= SYSCTL_RCGC2_GPIOA;
        SYSCTL_RCGC2_R |= SYSCTL_RCGC2_GPIOH;
-       __delay(512);
+       lm3s_busyWait(512);
 
        /* Configure the SSI0CLK and SSIOTX pins for SSI operation. */
        lm3s_gpio_pin_config(GPIO_PORTA_BASE, BV(2) | BV(3) | BV(5),