lm3s1968: make __delay() naked and usable outside the clock module.

In this way we're sure __delay() won't be inlined nor optimized by the
compiler and it can be used suitably as a simple spinning delay.

git-svn-id: https://src.develer.com/svnoss/bertos/trunk@3391 38d2e660-2303-0410-9eaa-f027e97ec537

diff --git a/bertos/cpu/cortex-m3/drv/clock_lm3s.c b/bertos/cpu/cortex-m3/drv/clock_lm3s.c
index 8790b0e6ed69319fcdbf3f644a2417f0d199811a..1c643b58c77cdc4599d729b64508e59b91333178 100644 (file)
--- a/bertos/cpu/cortex-m3/drv/clock_lm3s.c
+++ b/bertos/cpu/cortex-m3/drv/clock_lm3s.c
@@ -51,12 +51,15 @@
 /*
  * Very small delay: each loop takes 3 cycles.
  */
-INLINE void __delay(unsigned long iterations)
+void NAKED __delay(unsigned long iterations)
 {
+       register uint32_t __n asm("r0") = iterations;
+
        asm volatile (
-               "1:     subs    %0, #1\n\t"
-               "       bne 1b\n\t"
-               : "=r"(iterations) : : "memory", "cc");
+               "1: subs r0, #1\n\t"
+               "bne 1b\n\t"
+               "bx lr\n\t"
+               : : "r"(__n) : "memory", "cc");
 }
 
 unsigned long clock_get_rate(void)
@@ -110,6 +113,8 @@ void clock_set_rate(void)
        HWREG(SYSCTL_RCC) = rcc;
        HWREG(SYSCTL_RCC) = rcc2;
 
+       __delay(16);
+
        /*
         * Step #2: select the crystal value (XTAL) and oscillator source
         * (OSCSRC), and clear the PWRDN bit in RCC/RCC2. Setting the XTAL

diff --git a/bertos/cpu/cortex-m3/drv/clock_lm3s.h b/bertos/cpu/cortex-m3/drv/clock_lm3s.h
index d4322cc21871d7407153065acd0d6cc01eb53fa0..039401842f1b2cc5bbfccd98623e643f7ed7eef5 100644 (file)
--- a/bertos/cpu/cortex-m3/drv/clock_lm3s.h
+++ b/bertos/cpu/cortex-m3/drv/clock_lm3s.h
@@ -41,6 +41,8 @@
 /* Crystal frequency attached to the main oscillator. */
 #define XTAL_FREQ      SYSCTL_RCC_XTAL_8MHZ
 
+extern void __delay(unsigned long iterations);
+
 unsigned long clock_get_rate(void);
 void clock_set_rate(void);