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inline | side by side (from parent 1:
a997259)
SIGNAL(SIG_CTS)
{
// Re-enable UDR empty interrupt and TX, then disable CTS interrupt
SIGNAL(SIG_CTS)
{
// Re-enable UDR empty interrupt and TX, then disable CTS interrupt
- UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
+ UCSR0B = BV(BIT_RXCIE0) | BV(BIT_UDRIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0);
{
// Disable rx interrupt and tx, enable CTS interrupt
// UNTESTED
{
// Disable rx interrupt and tx, enable CTS interrupt
// UNTESTED
- UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN);
+ UCSR0B = BV(BIT_RXCIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0);
EIFR |= EIMSKF_CTS;
EIMSK |= EIMSKF_CTS;
}
EIFR |= EIMSKF_CTS;
EIMSK |= EIMSKF_CTS;
}
UARTDescs[SER_UART0].sending = false;
}
else
UARTDescs[SER_UART0].sending = false;
}
else
- UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
+ UCSR0B = BV(BIT_RXCIE0) | BV(BIT_UDRIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0);
{
// Disable rx interrupt and tx, enable CTS interrupt
// UNTESTED
{
// Disable rx interrupt and tx, enable CTS interrupt
// UNTESTED
- UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN);
+ UCSR1B = BV(BIT_RXCIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1);
EIFR |= EIMSKF_CTS;
EIMSK |= EIMSKF_CTS;
}
EIFR |= EIMSKF_CTS;
EIMSK |= EIMSKF_CTS;
}
UARTDescs[SER_UART1].sending = false;
}
else
UARTDescs[SER_UART1].sending = false;
}
else
- UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
+ UCSR1B = BV(BIT_RXCIE1) | BV(BIT_UDRIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1);