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inline | side by side (from parent 1:
e5ae58a)
void clock_set_rate(void)
{
reg32_t rcc, rcc2;
void clock_set_rate(void)
{
reg32_t rcc, rcc2;
int i;
rcc = HWREG(SYSCTL_RCC);
int i;
rcc = HWREG(SYSCTL_RCC);
* frequency for the microcontroller.
*/
rcc &= ~(SYSCTL_RCC_SYSDIV_M | SYSCTL_RCC_USESYSDIV);
* frequency for the microcontroller.
*/
rcc &= ~(SYSCTL_RCC_SYSDIV_M | SYSCTL_RCC_USESYSDIV);
- for (i = 0; i < 15; i++)
+
+ /*
+ * Try to evaluate the correct SYSDIV value depending on the desired
+ * CPU frequency.
+ */
+ clk = RCC_TO_CLK(rcc);
+ for (i = 0; i < 16; i++)
- if (CPU_FREQ == RCC_TO_CLK(rcc))
+ clk = clk / (i + 1);
+ if (CPU_FREQ >= clk)
- rcc |= SYSCTL_RCC_USESYSDIV;
+ {
+ rcc |= SYSCTL_RCC_USESYSDIV;
rcc |= i << SYSCTL_RCC_SYSDIV_SHIFT;
rcc |= i << SYSCTL_RCC_SYSDIV_SHIFT;
/*
* Step #4: wait for the PLL to lock by polling the PLLLRIS bit in the
/*
* Step #4: wait for the PLL to lock by polling the PLLLRIS bit in the