+/* End USART0 macros */
+
+#ifndef SER_UART1_IRQ_INIT
+ /** \sa SER_UART0_BUS_TXINIT */
+ #define SER_UART1_IRQ_INIT do { \
+ US1_IDR = 0xFFFFFFFF; \
+ /* Set the vector. */ \
+ AIC_SVR(US1_ID) = uart0_irq_dispatcher; \
+ /* Initialize to edge triggered with defined priority. */ \
+ AIC_SMR(US1_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED; \
+ /* Enable the USART IRQ */ \
+ AIC_IECR = BV(US1_ID); \
+ PMC_PCER = BV(US1_ID); \
+ } while (0)
+#endif
+
+#ifndef SER_UART1_BUS_TXINIT
+ /** \sa SER_UART1_BUS_TXINIT */
+ #if CPU_ARM_AT91
+ #define SER_UART1_BUS_TXINIT do { \
+ PIOA_PDR = BV(0) | BV(1); \
+ US1_CR = BV(US_RSTRX) | BV(US_RSTTX); \
+ US1_MR = US_CHMODE_NORMAL | US_CHRL_8 | US_NBSTOP_1; \
+ US1_CR = BV(US_RXEN) | BV(US_TXEN); \
+ US1_IER = BV(US_RXRDY); \
+ } while (0)
+ /*#elif Add other ARM families here */
+ #else
+ #error Unknown CPU
+ #endif
+
+#endif
+
+#ifndef SER_UART1_BUS_TXBEGIN
+ /** \sa SER_UART1_BUS_TXBEGIN */
+ #define SER_UART1_BUS_TXBEGIN do { \
+ US1_CR = BV(US_RXEN) | BV(US_TXEN); \
+ US1_IER = BV(US_TXRDY) | BV(US_RXRDY); \
+ } while (0)
+#endif
+
+#ifndef SER_UART1_BUS_TXCHAR
+ /** \sa SER_UART1_BUS_TXCHAR */
+ #define SER_UART1_BUS_TXCHAR(c) do { \
+ US1_THR = c; \
+ } while (0)
+#endif
+
+#ifndef SER_UART1_BUS_TXEND
+ /** \sa SER_UART1_BUS_TXEND */
+ #define SER_UART1_BUS_TXEND do { \
+ US1_CR = BV(US_RXEN) | BV(US_TXEN); \
+ US1_IER = BV(US_RXRDY); \
+ US1_IDR = BV(US_TXRDY); \
+ } while (0)
+#endif
+