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inline | side by side (from parent 1:
d6c4f61)
-/*
- * Set STOP condition bit, to send stop after next sent byte.
- */
-INLINE void setStop(I2c *i2c)
-{
- HWREG(i2c->hw->base + TWI_CR_OFF) = TWI_CR_STOP;
-}
/*
* The start is not performed when we call the start function
/*
* The start is not performed when we call the start function
HWREG(i2c->hw->base + TWI_THR_OFF) = data;
HWREG(i2c->hw->base + TWI_THR_OFF) = data;
+ if ((i2c->xfer_size == 1) && (I2C_TEST_STOP(i2c->flags) == I2C_STOP))
+ HWREG(i2c->hw->base + TWI_CR_OFF) = TWI_CR_STOP;
+
// On first byte sent wait for start timeout
if (i2c->hw->first_xtranf && !waitTxRdy(i2c, CONFIG_I2C_START_TIMEOUT))
{
LOG_ERR("i2c: write start timeout\n");
i2c->errors |= I2C_START_TIMEOUT;
// On first byte sent wait for start timeout
if (i2c->hw->first_xtranf && !waitTxRdy(i2c, CONFIG_I2C_START_TIMEOUT))
{
LOG_ERR("i2c: write start timeout\n");
i2c->errors |= I2C_START_TIMEOUT;
+ HWREG(i2c->hw->base + TWI_CR_OFF) = TWI_CR_STOP;
waitXferComplete(i2c);
return;
}
i2c->hw->first_xtranf = false;
if ((i2c->xfer_size == 1) && (I2C_TEST_STOP(i2c->flags) == I2C_STOP))
waitXferComplete(i2c);
return;
}
i2c->hw->first_xtranf = false;
if ((i2c->xfer_size == 1) && (I2C_TEST_STOP(i2c->flags) == I2C_STOP))
}
static uint8_t i2c_sam3_getc(I2c *i2c)
{
uint8_t data;
}
static uint8_t i2c_sam3_getc(I2c *i2c)
{
uint8_t data;
-
- if ((i2c->xfer_size == 1) && (I2C_TEST_STOP(i2c->flags) == I2C_STOP))
- setStop(i2c);
if (i2c->hw->first_xtranf)
{
if (i2c->hw->first_xtranf)
{
- HWREG(i2c->hw->base + TWI_CR_OFF) = TWI_CR_START;
i2c->hw->first_xtranf = false;
}
i2c->hw->first_xtranf = false;
}
+ if ((i2c->xfer_size == 1) && (I2C_TEST_STOP(i2c->flags) == I2C_STOP))
+ cr |= TWI_CR_STOP;
+
+ HWREG(i2c->hw->base + TWI_CR_OFF) = cr;
if (!waitRxRdy(i2c, CONFIG_I2C_START_TIMEOUT))
{
if (!waitRxRdy(i2c, CONFIG_I2C_START_TIMEOUT))
{
*/
void i2c_hw_init(I2c *i2c, int dev, uint32_t clock)
{
*/
void i2c_hw_init(I2c *i2c, int dev, uint32_t clock)
{
ASSERT(dev < I2C_CNT);
i2c->hw = &i2c_sam3_hw[dev];
i2c->vt = &i2c_sam3_vt;
ASSERT(dev < I2C_CNT);
i2c->hw = &i2c_sam3_hw[dev];
i2c->vt = &i2c_sam3_vt;
pmc_periphEnable(PIOA_ID);
switch (dev)
pmc_periphEnable(PIOA_ID);
switch (dev)
- /*
- * Reset sequence: enable slave mode, reset, read RHR,
- * disable slave and master modes.
- */
- HWREG(i2c->hw->base + TWI_CR_OFF) = TWI_CR_SVEN;
- HWREG(i2c->hw->base + TWI_CR_OFF) = TWI_CR_SWRST;
- dummy = HWREG(i2c->hw->base + TWI_RHR_OFF);
- HWREG(i2c->hw->base + TWI_CR_OFF) = TWI_CR_SVDIS;
- HWREG(i2c->hw->base + TWI_CR_OFF) = TWI_CR_MSDIS;
- // Set master mode
- HWREG(i2c->hw->base + TWI_CR_OFF) = TWI_CR_MSEN;
+ // Reset and set master mode
+ HWREG(i2c->hw->base + TWI_CR_OFF) = TWI_CR_SWRST;
+ HWREG(i2c->hw->base + TWI_CR_OFF) = TWI_CR_MSEN | TWI_CR_SVDIS;
i2c_setClock(i2c, clock);
}
i2c_setClock(i2c, clock);
}