Convert newlines to unix style.

git-svn-id: https://src.develer.com/svnoss/bertos/trunk@3388 38d2e660-2303-0410-9eaa-f027e97ec537

diff --git a/bertos/cpu/arm/hw/init_lpc2.c b/bertos/cpu/arm/hw/init_lpc2.c
index 7e03bf6ef358b4950d50db10ff72e00d18039b40..5f6ff507242335f4e48b027cc2b1b69b7bc8144d 100644 (file)
--- a/bertos/cpu/arm/hw/init_lpc2.c
+++ b/bertos/cpu/arm/hw/init_lpc2.c
@@ -33,11 +33,11 @@
  * \author Francesco Sacchi <batt@develer.com>
  *
  * \brief LPC2378 CRT.
- */\r
-#include <cpu/irq.h>\r
-\r
-#include <io/lpc23xx.h>\r
-\r
+ */
+#include <cpu/irq.h>
+
+#include <io/lpc23xx.h>
+
 #if CPU_FREQ != 72000000UL
        /* Avoid errors on nightly test */
        #if !defined(ARCH_NIGHTTEST) || !(ARCH & ARCH_NIGHTTEST)
@@ -52,70 +52,70 @@
 #define PLL_MUL_VAL  11
 #define PLL_DIV_VAL  0
 #define LPC2_CPUCLOCK_DIV 3
-\r
-\r
-/* PLL feed sequence */\r
-#define PLL_FEED_SEQ() ATOMIC(PLLFEED = 0xAA; PLLFEED = 0x55;)\r
-\r
-static void configurePll(void)\r
-{\r
-       /* Disconnect and disable the PLL, if already active */\r
-       if (PLLSTAT & (1 << 25))\r
-       {\r
-               /* Disconnect PLL, but leave it enabled */\r
-               PLLCON = 0x01;\r
-               PLL_FEED_SEQ();\r
-               /* Disable PLL */\r
-               PLLCON = 0;\r
-               PLL_FEED_SEQ();\r
-       }\r
-\r
-       /* Enable the main oscillator and wait for it to be stable */\r
-       SCS |= (1 << 5);\r
-    while (!(SCS & (1 << 6))) ;\r
-\r
-       /* Select the main oscillator as the PLL clock source */\r
-       CLKSRCSEL = 0x01;\r
-\r
-       /* Set up PLL mul and div */\r
-       PLLCFG = PLL_MUL_VAL | (PLL_DIV_VAL << 16);\r
-       PLL_FEED_SEQ();\r
-       \r
-       /* Enable PLL, disconnected */\r
-       PLLCON = 0x01;\r
-       PLL_FEED_SEQ();\r
-\r
-       /* Set clock divider */\r
-       CCLKCFG = LPC2_CPUCLOCK_DIV;\r
-\r
-       /* Wait for the PLL to lock */\r
-       while (!(PLLSTAT & (1 << 26))) ;\r
-    \r
-       /* Enable and connect the PLL */\r
-    PLLCON = 0x03;\r
-       PLL_FEED_SEQ();\r
-}\r
-\r
-void __init1(void);\r
-\r
-void __init1(void)\r
-{\r
-       /* Map irq vectors to internal flash */\r
-       MEMMAP = 0x01;\r
-       /* Configure PLL, switch from IRC to Main OSC */\r
-       configurePll();\r
-\r
-       /* Set memory accelerator module flash timings */\r
-#if CPU_FREQ < 20000000UL\r
-       MAMTIM = 1;\r
-#elif CPU_FREQ < 40000000UL\r
-       MAMTIM = 2;\r
-#elif CPU_FREQ < 60000000UL\r
-       MAMTIM = 3;\r
-#else\r
-       MAMTIM = 4;\r
-#endif\r
-       \r
-       /* Memory accelerator module fully enabled */\r
-       MAMCR = 0x02;\r
-}\r
+
+
+/* PLL feed sequence */
+#define PLL_FEED_SEQ() ATOMIC(PLLFEED = 0xAA; PLLFEED = 0x55;)
+
+static void configurePll(void)
+{
+       /* Disconnect and disable the PLL, if already active */
+       if (PLLSTAT & (1 << 25))
+       {
+               /* Disconnect PLL, but leave it enabled */
+               PLLCON = 0x01;
+               PLL_FEED_SEQ();
+               /* Disable PLL */
+               PLLCON = 0;
+               PLL_FEED_SEQ();
+       }
+
+       /* Enable the main oscillator and wait for it to be stable */
+       SCS |= (1 << 5);
+    while (!(SCS & (1 << 6))) ;
+
+       /* Select the main oscillator as the PLL clock source */
+       CLKSRCSEL = 0x01;
+
+       /* Set up PLL mul and div */
+       PLLCFG = PLL_MUL_VAL | (PLL_DIV_VAL << 16);
+       PLL_FEED_SEQ();
+       
+       /* Enable PLL, disconnected */
+       PLLCON = 0x01;
+       PLL_FEED_SEQ();
+
+       /* Set clock divider */
+       CCLKCFG = LPC2_CPUCLOCK_DIV;
+
+       /* Wait for the PLL to lock */
+       while (!(PLLSTAT & (1 << 26))) ;
+    
+       /* Enable and connect the PLL */
+    PLLCON = 0x03;
+       PLL_FEED_SEQ();
+}
+
+void __init1(void);
+
+void __init1(void)
+{
+       /* Map irq vectors to internal flash */
+       MEMMAP = 0x01;
+       /* Configure PLL, switch from IRC to Main OSC */
+       configurePll();
+
+       /* Set memory accelerator module flash timings */
+#if CPU_FREQ < 20000000UL
+       MAMTIM = 1;
+#elif CPU_FREQ < 40000000UL
+       MAMTIM = 2;
+#elif CPU_FREQ < 60000000UL
+       MAMTIM = 3;
+#else
+       MAMTIM = 4;
+#endif
+       
+       /* Memory accelerator module fully enabled */
+       MAMCR = 0x02;
+}