sam3x: add IAR-specific linker scripts

git-svn-id: https://src.develer.com/svnoss/bertos/trunk@4839 38d2e660-2303-0410-9eaa-f027e97ec537

diff --git a/bertos/cpu/cortex-m3/scripts/sam3x8_ram.icf b/bertos/cpu/cortex-m3/scripts/sam3x8_ram.icf
new file mode 100644 (file)
index 0000000..aeddad6
--- /dev/null
+++ b/bertos/cpu/cortex-m3/scripts/sam3x8_ram.icf
@@ -0,0 +1,52 @@
+/*-  SRAM0 memory region -*/
+define symbol __region_RAM0_size__          = 0x10000 ;
+define symbol __region_RAM0_start__         = 0x20000000 ;
+define symbol __region_RAM0_end__           = __region_RAM0_start__+__region_RAM0_size__-1 ;
+
+export symbol __region_RAM0_size__ ;
+export symbol __region_RAM0_start__ ;
+export symbol __region_RAM0_end__ ;
+
+/*-  SRAM1 memory region -*/
+define symbol __region_RAM1_size__          = 0x8000 ;
+define symbol __region_RAM1_start__         = 0x20080000 ;
+define symbol __region_RAM1_end__           = __region_RAM1_start__+__region_RAM1_size__-1 ;
+
+export symbol __region_RAM1_size__ ;
+export symbol __region_RAM1_start__ ;
+export symbol __region_RAM1_end__ ;
+
+/*- Continous SRAM region (SRAM0 is mirrored) -*/
+define symbol __region_RAM_size__           = __region_RAM0_size__+__region_RAM1_size__ ;
+define symbol __region_RAM_start__          = __region_RAM1_start__-__region_RAM0_size__ ;
+define symbol __region_RAM_end__            = __region_RAM1_end__ ;
+
+export symbol __region_RAM_size__ ;
+export symbol __region_RAM_start__ ;
+export symbol __region_RAM_end__ ;
+
+/*- NFC SRAM region -*/
+define symbol __region_NFC_RAM_start__      = 0x20100000 ;
+define symbol __region_NFC_RAM_end__        = 0x20100FFF ;
+
+export symbol __region_NFC_RAM_start__ ;
+export symbol __region_NFC_RAM_end__ ;
+
+/*-Vector table start*/
+define symbol __vector_start__              = __region_RAM_start__ ;
+
+/*-Sizes-*/
+define symbol __size_cstack__               = 0x2000 ;
+define symbol __size_heap__                 = 0x2000 ;
+
+define memory mem with size                 = 4G ;
+define region RAM_region                    = mem:[from __region_RAM_start__ to __region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __size_cstack__   { };
+define block HEAP      with alignment = 8, size = __size_heap__     { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__vector_start__ { readonly section .vectors };
+place in RAM_region          { readonly, readwrite, block CSTACK, block HEAP };

diff --git a/bertos/cpu/cortex-m3/scripts/sam3x8_rom.icf b/bertos/cpu/cortex-m3/scripts/sam3x8_rom.icf
new file mode 100644 (file)
index 0000000..5823a01
--- /dev/null
+++ b/bertos/cpu/cortex-m3/scripts/sam3x8_rom.icf
@@ -0,0 +1,71 @@
+/*-  SRAM0 memory region -*/
+define symbol __region_RAM0_size__          = 0x10000 ;
+define symbol __region_RAM0_start__         = 0x20000000 ;
+define symbol __region_RAM0_end__           = __region_RAM0_start__+__region_RAM0_size__-1 ;
+
+export symbol __region_RAM0_size__ ;
+export symbol __region_RAM0_start__ ;
+export symbol __region_RAM0_end__ ;
+
+/*-  SRAM1 memory region -*/
+define symbol __region_RAM1_size__          = 0x8000 ;
+define symbol __region_RAM1_start__         = 0x20080000 ;
+define symbol __region_RAM1_end__           = __region_RAM1_start__+__region_RAM1_size__-1 ;
+
+export symbol __region_RAM1_size__ ;
+export symbol __region_RAM1_start__ ;
+export symbol __region_RAM1_end__ ;
+
+/*- Continous SRAM region (SRAM0 is mirrored) -*/
+define symbol __region_RAM_size__           = __region_RAM0_size__+__region_RAM1_size__ ;
+define symbol __region_RAM_start__          = __region_RAM1_start__-__region_RAM0_size__ ;
+define symbol __region_RAM_end__            = __region_RAM1_end__ ;
+
+export symbol __region_RAM_size__ ;
+export symbol __region_RAM_start__ ;
+export symbol __region_RAM_end__ ;
+
+/*- NFC SRAM region -*/
+define symbol __region_NFC_RAM_start__      = 0x20100000 ;
+define symbol __region_NFC_RAM_end__        = 0x20100FFF ;
+
+export symbol __region_NFC_RAM_start__ ;
+export symbol __region_NFC_RAM_end__ ;
+
+/*- Flash region -*/
+define symbol __region_ROM_size__           = 0x00080000 ;
+define symbol __region_ROM_start__          = 0x00080000 ;
+define symbol __region_ROM_end__            = __region_ROM_start__+__region_ROM_size__-1 ;
+
+export symbol __region_ROM_size__ ;
+export symbol __region_ROM_start__ ;
+export symbol __region_ROM_end__ ;
+
+/*-Sizes-*/
+define symbol __size_cstack__               = 0x1000 ;
+define symbol __size_heap__                 = 0x1000 ;
+
+/* Size of the IRQ Stack (Main Stack).*/
+define symbol __ICFEDIT_size_irqstack__   = 0x1000 ;
+
+define memory mem with size                 = 4G ;
+define region RAM_region                    = mem:[from __region_RAM_start__ to __region_RAM_end__];
+define region ROM_region                    = mem:[from __region_ROM_start__ to __region_ROM_end__];
+
+define block CSTACK    with alignment = 8, size = __size_cstack__           {section CSTACK};
+define block IRQSTACK  with alignment = 8, size = __ICFEDIT_size_irqstack__ {};
+define block SYSHEAP   with alignment = 8                                   {section SYSHEAP};
+define block DATABSS   with alignment = 8 {readwrite, zeroinit};
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+keep { section .vtable };
+
+place at start of ROM_region                  {section .vtable};
+place in ROM_region                           {readonly};
+place at start of RAM_region                  {block IRQSTACK};
+place in RAM_region                           {block DATABSS};
+place in RAM_region                           {block SYSHEAP};
+place at end of RAM_region                    {block CSTACK};
+