#define CPU_RAM_START 0x60
#elif CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA168 || CPU_AVR_ATMEGA328P
#define CPU_RAM_START 0x100
- #elif CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280
+ #elif CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
#define CPU_RAM_START 0x200
#else
#warning Fix CPU_RAM_START address for your AVR, default value set to 0x100
#if CPU_AVR_ATMEGA8 || CPU_AVR_ATMEGA328P || CPU_AVR_ATMEGA168
ADMUX &= ~(BV(MUX3) | BV(MUX2) | BV(MUX1) | BV(MUX0));
#elif CPU_AVR_ATMEGA32 || CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA1281 \
- || CPU_AVR_ATMEGA1280
+ || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
ADMUX &= ~(BV(MUX4) | BV(MUX3) | BV(MUX2) | BV(MUX1) | BV(MUX0));
- #if CPU_AVR_ATMEGA1280
+ #if CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
ADCSRB &= ~(BV(MUX5));
#endif
#else
/* Select channel, only first 8 channel modes are supported */
ADMUX |= (ch & 0x07);
- #if CPU_AVR_ATMEGA1280
+ #if CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
/* Select channel, all 16 channels are supported */
if (ch > 0x07)
ADCSRB |= BV(MUX5);
#include <cfg/compiler.h>
-#if CPU_AVR_ATMEGA1280
+#if CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
/* 16 channels aivailable */
#define ADC_MUX_MAXCH 15
#else
* probably due to some unwanted interaction between the
* port pin and the TWI lines.
*/
- #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280
+ #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
PORTD |= BV(PD0) | BV(PD1);
DDRD |= BV(PD0) | BV(PD1);
#elif CPU_AVR_ATMEGA8
#endif
#if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280 \
- || CPU_AVR_ATMEGA168 || CPU_AVR_ATMEGA328P
+ || CPU_AVR_ATMEGA168 || CPU_AVR_ATMEGA328P || CPU_AVR_ATMEGA2560
#define UCR UCSR0B
#define UDR UDR0
#define USR UCSR0A
#error CONFIG_KDEBUG_PORT must be either 0 or 1
#endif
- #elif CPU_AVR_ATMEGA1280
+ #elif CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
#if CONFIG_KDEBUG_PORT == 0
UBRR0H = (uint8_t)(period>>8);
UBRR0L = (uint8_t)period;
/*\}*/
#endif
-#if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280
+#if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
#define BIT_RXCIE0 RXCIE0
#define BIT_RXEN0 RXEN0
#define BIT_TXEN0 TXEN0
#define BIT_RXEN1 RXEN1
#define BIT_TXEN1 TXEN1
#define BIT_UDRIE1 UDRIE1
- #if CPU_AVR_ATMEGA1280
+ #if CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
#define BIT_RXCIE2 RXCIE2
#define BIT_RXEN2 RXEN2
#define BIT_TXEN2 TXEN2
/* SPI port and pin configuration */
#if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103 || CPU_AVR_ATMEGA1281 \
- || CPU_AVR_ATMEGA1280
+ || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
#define SPI_PORT PORTB
#define SPI_DDR DDRB
#define SPI_SS_BIT PB0
#endif
/* USART register definitions */
-#if CPU_AVR_ATMEGA1280
+#if CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
#define AVR_HAS_UART1 1
#define AVR_HAS_UART2 1
#define AVR_HAS_UART3 1
*/
enum
{
-#if CPU_AVR_ATMEGA1280
+#if CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
SER_UART0,
SER_UART1,
SER_UART2,
#include <avr/io.h>
-#if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA168 || CPU_AVR_ATMEGA328P
+#if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA168 || CPU_AVR_ATMEGA328P || CPU_AVR_ATMEGA2560
#define REG_TIFR0 TIFR0
#define REG_TIFR1 TIFR1
#define REG_TIFR2 TIFR2
- #if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280
+ #if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
#define REG_TIFR3 TIFR3
#endif
#define REG_TIMSK0 TIMSK0
#define REG_TIMSK1 TIMSK1
#define REG_TIMSK2 TIMSK2
- #if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280
+ #if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
#define REG_TIMSK3 TIMSK3
#endif
#define TIMER_PRESCALER 64
#define TIMER_HW_BITS 8
- #if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA168 || CPU_AVR_ATMEGA328P
+ #if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA168 || CPU_AVR_ATMEGA328P || CPU_AVR_ATMEGA2560
#define DEFINE_TIMER_ISR DECLARE_ISR_CONTEXT_SWITCH(TIMER0_COMPA_vect)
#else
#define DEFINE_TIMER_ISR DECLARE_ISR_CONTEXT_SWITCH(TIMER0_COMP_vect)
#define TIMER_PRESCALER 64
#define TIMER_HW_BITS 8
- #if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA168 || CPU_AVR_ATMEGA328P
+ #if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA168 || CPU_AVR_ATMEGA328P || CPU_AVR_ATMEGA2560
#define DEFINE_TIMER_ISR DECLARE_ISR_CONTEXT_SWITCH(TIMER2_COMPA_vect)
#else
#define DEFINE_TIMER_ISR DECLARE_ISR_CONTEXT_SWITCH(TIMER2_COMP_vect)
#define CPU_AVR_ATMEGA1280 0
#endif
+ #if defined(__AVR_ATmega2560__)
+ #define CPU_AVR_ATMEGA2560 1
+ #define CPU_NAME "ATmega2560"
+ #else
+ #define CPU_AVR_ATMEGA2560 0
+ #endif
+
#if CPU_AVR_ATMEGA32 + CPU_AVR_ATMEGA64 + CPU_AVR_ATMEGA103 + CPU_AVR_ATMEGA128 \
+ CPU_AVR_ATMEGA8 + CPU_AVR_ATMEGA168 + CPU_AVR_ATMEGA328P + CPU_AVR_ATMEGA1281 \
- + CPU_AVR_ATMEGA1280 != 1
+ + CPU_AVR_ATMEGA1280 + CPU_AVR_ATMEGA2560 != 1
#error AVR CPU configuration error
#endif
#else
#define CPU_AVR_ATMEGA128 0
#define CPU_AVR_ATMEGA1281 0
#define CPU_AVR_ATMEGA1280 0
+ #define CPU_AVR_ATMEGA2560 0
#endif
#if defined (__MSP430__)