AT91SAM7: add FMCN shifts.

git-svn-id: https://src.develer.com/svnoss/bertos/trunk@3380 38d2e660-2303-0410-9eaa-f027e97ec537

diff --git a/bertos/cpu/arm/io/at91_mc.h b/bertos/cpu/arm/io/at91_mc.h
index fbae705e80332e7347ca4759cf2bf9b446563642..735bc4102003fee30c2a13514f0d03f33b3be59e 100644 (file)
--- a/bertos/cpu/arm/io/at91_mc.h
+++ b/bertos/cpu/arm/io/at91_mc.h
@@ -109,6 +109,7 @@
 #define MC_FWS_3R4W             0x00000200      ///< 3 cycles for read, 4 for write operations.
 #define MC_FWS_4R4W             0x00000300      ///< 4 cycles for read and write operations.
 #define MC_FMCN_MASK            0x00FF0000      ///< Flash microsecond cycle number mask.
+#define MC_FMCN_SHIFT                   16      ///< Flash microsecond cycle number shift.
 
 #define MC_FCR_OFF              0x00000064      ///< MC flash command register offset.
 #define MC_FCR      (*((reg32_t *)(MC_BASE + MC_FCR_OFF)))      ///< MC flash command register address.