SAM3: fix mismatched UART and USART I/O pin assignment for all SAM3 cpus

git-svn-id: https://src.develer.com/svnoss/bertos/trunk@4723 38d2e660-2303-0410-9eaa-f027e97ec537

diff --git a/bertos/cpu/cortex-m3/drv/kdebug_sam3.c b/bertos/cpu/cortex-m3/drv/kdebug_sam3.c
index 3438c05c3877318e0a71f2ba06d4323b6215af1c..c00acdd5f2639f2079b0e88012769d8c381e6684 100644 (file)
--- a/bertos/cpu/cortex-m3/drv/kdebug_sam3.c
+++ b/bertos/cpu/cortex-m3/drv/kdebug_sam3.c
@@ -45,12 +45,12 @@
        #define UART_BASE       UART0_BASE
        #define UART_ID         UART0_ID
        #define UART_PIO_BASE   PIOA_BASE
-       #define UART_PINS       (BV(RXD0) | BV(TXD0))
-#elif (CONFIG_KDEBUG_PORT == 1) && !defined(CPU_CM3_SAM3U)
+       #define UART_PINS       (BV(URXD0) | BV(UTXD0))
+#elif (CONFIG_KDEBUG_PORT == 1) && UART_PORTS > 1
        #define UART_BASE       UART1_BASE
        #define UART_ID         UART1_ID
        #define UART_PIO_BASE   PIOB_BASE
-       #define UART_PINS       (BV(RXD1) | BV(TXD1))
+       #define UART_PINS       (BV(URXD1) | BV(UTXD1))
 #else
        #error "UART port not supported in this board"
 #endif

diff --git a/bertos/cpu/cortex-m3/drv/ser_sam3.c b/bertos/cpu/cortex-m3/drv/ser_sam3.c
index b6f6eae543d910c956e9c33305f25fc55ab42220..e7835bc314fb38b0c8251558c8702eb3f4664f79 100644 (file)
--- a/bertos/cpu/cortex-m3/drv/ser_sam3.c
+++ b/bertos/cpu/cortex-m3/drv/ser_sam3.c
@@ -119,7 +119,7 @@
 
 /* End USART0 macros */
 
-#if !CPU_CM3_SAM3U
+#if USART_PORTS > 1
 
        #ifndef SER_UART1_BUS_TXINIT
                /**
@@ -127,20 +127,12 @@
                 *
                 * - Disable GPIO on USART1 tx/rx pins
                 */
-               #if CPU_ARM_AT91
-                       #if !CPU_ARM_SAM7S_LARGE && !CPU_ARM_SAM7X
-                               #warning Check USART1 pins!
-                       #endif
-                       #define SER_UART1_BUS_TXINIT do { \
-                               PIOA_PDR = BV(RXD1) | BV(TXD1); \
-                       } while (0)
-               #elif CPU_CM3_SAM3
-                       #define SER_UART1_BUS_TXINIT do { \
-                               PIOB_PDR = BV(RXD1) | BV(TXD1); \
-                       } while (0)
-               #else
-                       #error Unknown CPU
+               #if CPU_ARM_AT91 && !CPU_ARM_SAM7S_LARGE && !CPU_ARM_SAM7X
+                       #warning Check USART1 pins!
                #endif
+               #define SER_UART1_BUS_TXINIT do { \
+                       PIOA_PDR = BV(RXD1) | BV(TXD1); \
+               } while (0)
        #endif
 
        #ifndef SER_UART1_BUS_TXBEGIN
@@ -296,7 +288,7 @@ extern struct Serial *ser_handles[SER_CNT];
 /* TX and RX buffers */
 static unsigned char uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
 static unsigned char uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
-#if !CPU_CM3_SAM3U
+#if USART_PORTS > 1
 static unsigned char uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
 static unsigned char uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
 #endif
@@ -330,7 +322,7 @@ struct ArmSerial
 };
 
 static ISR_PROTO(uart0_irq_dispatcher);
-#if !CPU_CM3_SAM3U
+#if USART_PORTS > 1
 static ISR_PROTO(uart1_irq_dispatcher);
 #endif
 static ISR_PROTO(spi0_irq_handler);
@@ -427,6 +419,9 @@ static void uart0_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity
                        ASSERT(0);
        }
 }
+
+#if USART_PORTS > 1
+
 /*
  * Callbacks for USART1
  */
@@ -518,6 +513,8 @@ static void uart1_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity
        }
 }
 
+#endif /* USART_PORTS > 1 */
+
 /* SPI driver */
 static void spi0_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct Serial *, ser))
 {
@@ -709,6 +706,8 @@ static const struct SerialHardwareVT UART0_VT =
        C99INIT(txSending, tx_sending),
 };
 
+#if USART_PORTS > 1
+
 static const struct SerialHardwareVT UART1_VT =
 {
        C99INIT(init, uart1_init),
@@ -719,6 +718,8 @@ static const struct SerialHardwareVT UART1_VT =
        C99INIT(txSending, tx_sending),
 };
 
+#endif /* USART_PORTS > 1 */
+
 static const struct SerialHardwareVT SPI0_VT =
 {
        C99INIT(init, spi0_init),
@@ -752,6 +753,7 @@ static struct ArmSerial UARTDescs[SER_CNT] =
                },
                C99INIT(sending, false),
        },
+#if USART_PORTS > 1
        {
                C99INIT(hw, /**/) {
                        C99INIT(table, &UART1_VT),
@@ -762,6 +764,7 @@ static struct ArmSerial UARTDescs[SER_CNT] =
                },
                C99INIT(sending, false),
        },
+#endif
 
        {
                C99INIT(hw, /**/) {
@@ -857,6 +860,8 @@ static DECLARE_ISR(uart0_irq_dispatcher)
        SER_INT_ACK;
 }
 
+#if USART_PORTS > 1
+
 /**
  * Serial 1 TX interrupt handler
  */
@@ -920,6 +925,8 @@ static DECLARE_ISR(uart1_irq_dispatcher)
        SER_INT_ACK;
 }
 
+#endif /* USART_PORTS > 1 */
+
 /**
  * SPI0 interrupt handler
  */

diff --git a/bertos/cpu/cortex-m3/io/sam3.h b/bertos/cpu/cortex-m3/io/sam3.h
index 8e66d1e81cbab4c85fe690bbf7132cdcee97ee61..429c3d5e75cfdf1a3737d93a29b4038f007e2a0f 100644 (file)
--- a/bertos/cpu/cortex-m3/io/sam3.h
+++ b/bertos/cpu/cortex-m3/io/sam3.h
@@ -127,6 +127,16 @@
 #define USART_HAS_PDC  1
 #define SPI_HAS_PDC    1
 
+#if CPU_CM3_SAM3X || CPU_CM3_SAM3U
+       #define USART_PORTS    1
+       #define UART_PORTS     4
+#elif CPU_CM3_SAM3N || CPU_CM3_SAM3S
+       #define USART_PORTS    2
+       #define UART_PORTS     2
+#else
+       #error undefined U(S)ART_PORTS for this cpu
+#endif
+
 /* PDC registers */
 #define PERIPH_RPR_OFF  0x100  // Receive Pointer Register.
 #define PERIPH_RCR_OFF  0x104  // Receive Counter Register.
@@ -157,20 +167,40 @@
 #include "sam3_wdt.h"
 
 /**
- * UART I/O pins
+ * U(S)ART I/O pins
  */
 /*\{*/
 #if CPU_CM3_SAM3U
-       #define RXD0   11
-       #define TXD0   12
+       #define URXD0   11  // Port A
+       #define UTXD0   12  // Port A
+       #define RXD0    19  // Port A
+       #define TXD0    18  // Port A
+       #define RXD1    21  // Port A
+       #define TXD1    20  // Port A
+       #define RXD2    23  // Port A
+       #define TXD2    22  // Port A
+       #define RXD3    13  // Port C
+       #define TXD3    12  // Port C
 #elif CPU_CM3_SAM3X
-       #define RXD0    8
-       #define TXD0    9
-#else
-       #define RXD0    9
-       #define TXD0   10
-       #define RXD1    2
-       #define TXD1    3
+       #define URXD0    8  // Port A
+       #define UTXD0    9  // Port A
+       #define RXD0    10  // Port A
+       #define TXD0    11  // Port A
+       #define RXD1    12  // Port A
+       #define TXD1    13  // Port A
+       #define RXD2    21  // Port B
+       #define TXD2    20  // Port B
+       #define RXD3     5  // Port D
+       #define TXD3     4  // Port D
+#elif CPU_CM3_SAM3N || CPU_CM3_SAM3S
+       #define URXD0    9  // Port A
+       #define UTXD0   10  // Port A
+       #define URXD1    2  // Port B
+       #define UTXD1    3  // Port B
+       #define RXD0     5  // Port A
+       #define TXD0     6  // Port A
+       #define RXD1    21  // Port A
+       #define TXD1    22  // Port A
 #endif
 /*\}*/