LPC2: add init module.

git-svn-id: https://src.develer.com/svnoss/bertos/trunk@3385 38d2e660-2303-0410-9eaa-f027e97ec537

diff --git a/bertos/cpu/arm/hw/init_lpc2.c b/bertos/cpu/arm/hw/init_lpc2.c
new file mode 100644 (file)
index 0000000..7e03bf6
--- /dev/null
+++ b/bertos/cpu/arm/hw/init_lpc2.c
@@ -0,0 +1,121 @@
+/**
+ * \file
+ * <!--
+ * This file is part of BeRTOS.
+ *
+ * Bertos is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ *
+ * As a special exception, you may use this file as part of a free software
+ * library without restriction.  Specifically, if other files instantiate
+ * templates or use macros or inline functions from this file, or you compile
+ * this file and link it with other files to produce an executable, this
+ * file does not by itself cause the resulting executable to be covered by
+ * the GNU General Public License.  This exception does not however
+ * invalidate any other reasons why the executable file might be covered by
+ * the GNU General Public License.
+ *
+ * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
+ *
+ * -->
+ *
+ * \author Francesco Sacchi <batt@develer.com>
+ *
+ * \brief LPC2378 CRT.
+ */\r
+#include <cpu/irq.h>\r
+\r
+#include <io/lpc23xx.h>\r
+\r
+#if CPU_FREQ != 72000000UL
+       /* Avoid errors on nightly test */
+       #if !defined(ARCH_NIGHTTEST) || !(ARCH & ARCH_NIGHTTEST)
+               #warning Clock registers set for 72MHz operation, revise following code if you want a different clock.
+       #endif
+#endif
+
+/*
+ * With a 12MHz cristal, master clock is:
+ * (((2 * 12 * (PLL_MUL_VAL + 1)) / (PLL_DIV_VAL + 1)) / (LPC2_CPUCLOCK_DIV + 1))= 72MHz
+ */
+#define PLL_MUL_VAL  11
+#define PLL_DIV_VAL  0
+#define LPC2_CPUCLOCK_DIV 3
+\r
+\r
+/* PLL feed sequence */\r
+#define PLL_FEED_SEQ() ATOMIC(PLLFEED = 0xAA; PLLFEED = 0x55;)\r
+\r
+static void configurePll(void)\r
+{\r
+       /* Disconnect and disable the PLL, if already active */\r
+       if (PLLSTAT & (1 << 25))\r
+       {\r
+               /* Disconnect PLL, but leave it enabled */\r
+               PLLCON = 0x01;\r
+               PLL_FEED_SEQ();\r
+               /* Disable PLL */\r
+               PLLCON = 0;\r
+               PLL_FEED_SEQ();\r
+       }\r
+\r
+       /* Enable the main oscillator and wait for it to be stable */\r
+       SCS |= (1 << 5);\r
+    while (!(SCS & (1 << 6))) ;\r
+\r
+       /* Select the main oscillator as the PLL clock source */\r
+       CLKSRCSEL = 0x01;\r
+\r
+       /* Set up PLL mul and div */\r
+       PLLCFG = PLL_MUL_VAL | (PLL_DIV_VAL << 16);\r
+       PLL_FEED_SEQ();\r
+       \r
+       /* Enable PLL, disconnected */\r
+       PLLCON = 0x01;\r
+       PLL_FEED_SEQ();\r
+\r
+       /* Set clock divider */\r
+       CCLKCFG = LPC2_CPUCLOCK_DIV;\r
+\r
+       /* Wait for the PLL to lock */\r
+       while (!(PLLSTAT & (1 << 26))) ;\r
+    \r
+       /* Enable and connect the PLL */\r
+    PLLCON = 0x03;\r
+       PLL_FEED_SEQ();\r
+}\r
+\r
+void __init1(void);\r
+\r
+void __init1(void)\r
+{\r
+       /* Map irq vectors to internal flash */\r
+       MEMMAP = 0x01;\r
+       /* Configure PLL, switch from IRC to Main OSC */\r
+       configurePll();\r
+\r
+       /* Set memory accelerator module flash timings */\r
+#if CPU_FREQ < 20000000UL\r
+       MAMTIM = 1;\r
+#elif CPU_FREQ < 40000000UL\r
+       MAMTIM = 2;\r
+#elif CPU_FREQ < 60000000UL\r
+       MAMTIM = 3;\r
+#else\r
+       MAMTIM = 4;\r
+#endif\r
+       \r
+       /* Memory accelerator module fully enabled */\r
+       MAMCR = 0x02;\r
+}\r