sam3: add missing SMC register definition.

git-svn-id: https://src.develer.com/svnoss/bertos/trunk@4833 38d2e660-2303-0410-9eaa-f027e97ec537

diff --git a/bertos/cpu/cortex-m3/io/sam3_smc.h b/bertos/cpu/cortex-m3/io/sam3_smc.h
index b6679b03aeef9dab759ac5387c09e237ba0a50d1..ab915f4f1d0f0dd92d967fb926c070b93d01f9f3 100644 (file)
--- a/bertos/cpu/cortex-m3/io/sam3_smc.h
+++ b/bertos/cpu/cortex-m3/io/sam3_smc.h
@@ -248,6 +248,32 @@
 #define SMC_CYCLE_NRD_CYCLE(x)        (SMC_CYCLE_NRD_CYCLE_MASK & ((x) << SMC_CYCLE_NRD_CYCLE_SHIFT))
 /*\}*/
 
+/**
+ * Defines for bit fields in SMC_TIMINGS registers.
+ */
+/*\{*/
+#define SMC_TIMINGS_TCLR_SHIFT     0
+#define SMC_TIMINGS_TCLR_MASK      (0xf << SMC_TIMINGS_TCLR_SHIFT)
+#define SMC_TIMINGS_TCLR(value)    (SMC_TIMINGS_TCLR_MASK & ((value) << SMC_TIMINGS_TCLR_SHIFT))
+#define SMC_TIMINGS_TADL_SHIFT     4
+#define SMC_TIMINGS_TADL_MASK      (0xf << SMC_TIMINGS_TADL_SHIFT)
+#define SMC_TIMINGS_TADL(value)    (SMC_TIMINGS_TADL_MASK & ((value) << SMC_TIMINGS_TADL_SHIFT))
+#define SMC_TIMINGS_TAR_SHIFT      8
+#define SMC_TIMINGS_TAR_MASK       (0xf << SMC_TIMINGS_TAR_SHIFT)
+#define SMC_TIMINGS_TAR(value)     (SMC_TIMINGS_TAR_MASK & ((value) << SMC_TIMINGS_TAR_SHIFT))
+#define SMC_TIMINGS_OCMS           BV(12)
+#define SMC_TIMINGS_TRR_SHIFT      16
+#define SMC_TIMINGS_TRR_MASK       (0xf << SMC_TIMINGS_TRR_SHIFT)
+#define SMC_TIMINGS_TRR(value)     (SMC_TIMINGS_TRR_MASK & ((value) << SMC_TIMINGS_TRR_SHIFT))
+#define SMC_TIMINGS_TWB_SHIFT      24
+#define SMC_TIMINGS_TWB_MASK       (0xf << SMC_TIMINGS_TWB_SHIFT)
+#define SMC_TIMINGS_TWB(value)     (SMC_TIMINGS_TWB_MASK & ((value) << SMC_TIMINGS_TWB_SHIFT))
+#define SMC_TIMINGS_RBNSEL_SHIFT   28
+#define SMC_TIMINGS_RBNSEL_MASK    (0x7 << SMC_TIMINGS_RBNSEL_SHIFT)
+#define SMC_TIMINGS_RBNSEL(value)  (SMC_TIMINGS_RBNSEL_MASK & ((value) << SMC_TIMINGS_RBNSEL_SHIFT))
+#define SMC_TIMINGS_NFSEL          BV(31)
+/*\}*/
+
 /**
  * Defines for bit fields in SMC_MODE registers.
  */