* independently.
* However, there are a few sources called "system sources" that
* share a common IRQ line and vector, called "system IRQ".
- * So a unique system IRQ handler is implemented here.
+ * So a unique system IRQ dispatcher is implemented here.
* This module also contains an interface to manage every source
* independently. It is possible to assign to every system IRQ
* a specific IRQ handler.
*/
#include "sysirq.h"
-#include "at91.h"
+#include "at91sam7s.h"
#include <cfg/cpu.h>
-
-#warning Very untested!
+#include <cfg/module.h>
+#include <cfg/macros.h>
/**
* Enable/disable the Periodic Interrupt Timer
* interrupt.
*/
-INLINE static void pit_setEnable(bool enable)
+INLINE void pit_setEnable(bool enable)
{
if (enable)
PIT_MR |= BV(PITIEN);
static void sysirq_dispatcher(void)
{
#warning TODO add IRQ prologue/epilogue
- for (int i = 0; i < countof(sysirq_tab); i++)
+ for (unsigned i = 0; i < countof(sysirq_tab); i++)
{
if (sysirq_tab[i].enabled
&& sysirq_tab[i].handler)
IRQ_SAVE_DISABLE(flags);
/* Disable all system interrupts */
- for (int i = 0; i < countof(sysirq_tab); i++)
+ for (unsigned i = 0; i < countof(sysirq_tab); i++)
sysirq_tab[i].setEnable(false);
/* Set the vector. */
- AIC_SVR(SYSC_ID) = sysirq_handler;
+ AIC_SVR(SYSC_ID) = sysirq_dispatcher;
/* Initialize to edge triggered with defined priority. */
- AIC_SMR(SYSC_ID) = BV(AIC_SRCTYPE_INT_EDGE_TRIGGERED) | SYSIRQ_PRIORITY;
+ AIC_SMR(SYSC_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED | SYSIRQ_PRIORITY;
/* Clear interrupt */
AIC_ICCR = BV(SYSC_ID);
ASSERT(irq < SYSIRQ_CNT);
sysirq_tab[irq].setEnable(enable);
- sysirq_enabled = enable;
+ sysirq_tab[irq].enabled = enable;
}
/**
{
ASSERT(irq >= 0);
ASSERT(irq < SYSIRQ_CNT);
+
return sysirq_tab[irq].enabled;
}
#ifndef DRV_AT91_SYSIRQ_H
#define DRV_AT91_SYSIRQ_H
+#include <cfg/compiler.h>
+
typedef void (* sysirq_handler_t)(void); ///< Type for system irq handler.
typedef void (* sysirq_setEnable_t)(bool); ///< Type for system irq enable/disable function.
* \brief Low-level timer module for Atmel AT91 (inplementation).
*/
-#include <drv/timer_at91.h>
-#include <cfg/macros.h> // BV()
+#include "timer.h"
+#include "at91sam7s.h"
+#include "sysirq.h"
+#include <cfg/macros.h> // BV()
+#include <cfg/module.h>
#include <cfg/cpu.h>
/** HW dependent timer initialization */
#if (CONFIG_TIMER == TIMER_ON_PIT)
- #warning Very untested!
- INLINE static void timer_hw_irq(void)
+ INLINE void timer_hw_irq(void)
{
/* Reset counters, this is needed to reset timer and interrupt flags */
- volatile uint32_t dummy = PIT_PIVR;
+ uint32_t dummy = PIVR;
+ (void) dummy;
}
- INLINE static bool timer_hw_triggered(void)
+ INLINE bool timer_hw_triggered(void)
{
return PIT_SR & BV(PITS);
}
- INLINE static void timer_hw_init(void)
+ INLINE void timer_hw_init(void)
{
cpuflags_t flags;
+
+ MOD_CHECK(sysirq);
+
IRQ_SAVE_DISABLE(flags);
- PIT_MR = CLOCK_FREQ / (16 * TIMER_TICKS_PER_SEC) - 1;
+ PIT_MR = TIMER_HW_CNT;
/* Register system interrupt handler. */
sysirq_setHandler(SYSIRQ_PIT, timer_handler);
/* Enable interval timer and interval timer interrupts */
- PIT_MR |= BV(PIT_PITEN);
+ PIT_MR |= BV(PITEN);
sysirq_setEnable(SYSIRQ_PIT, true);
/* Reset counters, this is needed to start timer and interrupt flags */
- volatile uint32_t dummy = PIT_PIVR;
+ uint32_t dummy = PIVR;
+ (void) dummy;
IRQ_RESTORE(flags);
}
- INLINE static hptime_t timer_hw_hpread(void)
+ INLINE hptime_t timer_hw_hpread(void)
{
/* In the upper part of PIT_PIIR there is unused data */
- return PIT_PIIR & 0xfffff;
+ return PIIR & CPIV_MASK;
}
#else
*/
#if (CONFIG_TIMER == TIMER_ON_PIT)
+ void timer_handler(void);
+
#define DEFINE_TIMER_ISR void timer_handler(void)
#define TIMER_TICKS_PER_SEC 1000
- #define TIMER_HW_CNT FIXME
+ #define TIMER_HW_CNT (CLOCK_FREQ / (16 * TIMER_TICKS_PER_SEC) - 1)
+
+ /** Frequency of the hardware high-precision timer. */
+ #define TIMER_HW_HPTICKS_PER_SEC (CLOCK_FREQ / 16)
/// Type of time expressed in ticks of the hardware high-precision timer
typedef uint32_t hptime_t;
#error Unimplemented value for CONFIG_TIMER
#endif /* CONFIG_TIMER */
-/** Frequency of the hardware high-precision timer. */
-#define TIMER_HW_HPTICKS_PER_SEC FIXME
#endif /* DRV_TIMER_AT91_H */