STM32: correctly set PCLK1 to 36MHz (max allowed frequency).

git-svn-id: https://src.develer.com/svnoss/bertos/trunk@3669 38d2e660-2303-0410-9eaa-f027e97ec537

diff --git a/bertos/cpu/cortex-m3/drv/clock_stm32.c b/bertos/cpu/cortex-m3/drv/clock_stm32.c
index 4b8cd89897de9982210badca6b9ccf3d5eefacc3..c225da8d767175e702764e1ca7ce03485db7839d 100644 (file)
--- a/bertos/cpu/cortex-m3/drv/clock_stm32.c
+++ b/bertos/cpu/cortex-m3/drv/clock_stm32.c
@@ -136,7 +136,7 @@ void clock_init(void)
        RCC->CFGR |= RCC_HCLK_DIV1 << 3;
        /* Configure system clock dividers: PCLK1 (36MHz) */
        RCC->CFGR &= CFGR_PPRE1_RESET_MASK;
-       RCC->CFGR |= RCC_HCLK_DIV2 << 3;
+       RCC->CFGR |= RCC_HCLK_DIV2;
        /* Configure system clock dividers: HCLK */
        RCC->CFGR &= CFGR_HPRE_RESET_MASK;
        RCC->CFGR |= RCC_SYSCLK_DIV1;