Update hw template for sipo module.

git-svn-id: https://src.develer.com/svnoss/bertos/trunk@2831 38d2e660-2303-0410-9eaa-f027e97ec537

diff --git a/bertos/hw/hw_sipo.h b/bertos/hw/hw_sipo.h
index b8d4e049ca8ab121a800faaa82edec9b85464e66..0b5699417fffc623235e5cd6499de21bb4e0315a 100644 (file)
--- a/bertos/hw/hw_sipo.h
+++ b/bertos/hw/hw_sipo.h
@@ -43,80 +43,55 @@
 #ifndef HW_SIPO_H
 #define HW_SIPO_H
 
-#warning TODO:This is an example implementation, you must implement it!
-
-
 /**
- * Mapping sipo connection on board.
- * See scheme to more info.
+ * Define generic macro to set pins logic level
  */
-typedef enum SipoMap {
-
-       /* Add device here */
-
-       SIPO_CNT
-} SipoMap;
+#define SIPO_SET_LEVEL_LOW(dev)    do { /* Implement me! */   } while (0)
+#define SIPO_SET_LEVEL_HIGH(dev)   do { /* Implement me! */   } while (0)
 
 
 /**
- * Define the macros needed to set the serial input bit of SIPO device
- * low or high.
+ * Generate one low pulse on select line.
  */
-#define SIPO_SI_HIGH() do { /* Implement me! */ } while (0)
-#define SIPO_SI_LOW()  do { /* Implement me! */ } while (0)
+#define PULSE_LOW(dev)    do { /* Implement me! */   } while (0)
 
 /**
- * Drive pin to load the bit, presented in serial-in pin,
- * into sipo shift register.
+ * Generate one hight pulse on select line.
  */
-#define SIPO_SI_CLOCK(clk_pol) \
-       do { \
-               /* Implement me! */ \
-               (void)clk_pol; \
-       } while (0)
+#define PULSE_HIGH(dev)     do { /* Implement me! */   } while (0)
+
 
 /**
- * Clock the content of shift register to output.
+ * Define the procedure to drive serial input in sipo device (SI).
  */
-#define SIPO_LOAD(device, load_pol)  \
-       do { \
-               /* Implement me! */ \
-               (void)device; \
-               (void)load_pol; \
-       } while (0)
+#define SIPO_SI_HIGH()   do { /* Implement me! */   } while (0)
+#define SIPO_SI_LOW()    do { /* Implement me! */   } while (0)
 
 /**
- * Enable the shift register output.
+ * Drive clock to shift SI data into latch.
  */
-#define SIPO_ENABLE() /* Implement me! */
+#define SIPO_SI_CLOCK(clk_pol)       do { /* Implement me! */   } while (0)
 
 /**
- * Set logic level for load signal
+ * Do everything needed in order to load dato into sipo.
  */
-#define SIPO_SET_LD_LEVEL(device, load_pol) \
-       do { \
-               /* Implement me! */ \
-               (void)device; \
-               (void)load_pol; \
-       } while (0)
-
+#define SIPO_LOAD(device, load_pol)   do { /* Implement me! */   } while (0)
 
 /**
- * Sel logic level for clock signal
+ * Enable the shift register output.
  */
-#define SIPO_SET_CLK_LEVEL(clock_pol)  \
-       do { \
-               /* Implement me! */ \
-               (void)clock_pol; \
-       } while (0)
+#define SIPO_ENABLE()             do { /* Implement me! */   } while (0)
 
+/**
+ * Set polarity for Load, Clk, SI signals.
+ */
+#define SIPO_SET_LD_LEVEL(device, load_pol)  do { /* Implement me! */   } while (0)
+#define SIPO_SET_CLK_LEVEL(clock_pol)        do { /* Implement me! */   } while (0)
+#define SIPO_SET_SI_LEVEL()       do { /* Implement me! */   } while (0)
 
 /**
- * Do everything needed in order to init the SIPO pins.
+ * Do anything that needed to init sipo pins.
  */
-#define SIPO_INIT_PIN() \
-       do { \
-               /* Implement me! */ \
-       } while(0)
+#define SIPO_INIT_PIN()           do { /* Implement me! */   } while (0)
 
 #endif /* HW_SIPO_H */