Fix some pastos

git-svn-id: https://src.develer.com/svnoss/bertos/trunk@4254 38d2e660-2303-0410-9eaa-f027e97ec537

diff --git a/bertos/cpu/cortex-m3/io/sam3_memmap.h b/bertos/cpu/cortex-m3/io/sam3_memmap.h
index 7ceb219637a747c70c15d35f13c39c3f23397076..987bae901f28bc7e200046664bf1009cfa07ea21 100644 (file)
--- a/bertos/cpu/cortex-m3/io/sam3_memmap.h
+++ b/bertos/cpu/cortex-m3/io/sam3_memmap.h
@@ -33,8 +33,8 @@
  * \brief AT91SAM3 memory map.
  */
 
-#ifndef STM32_MEMMAP_H
-#define STM32_MEMMAP_H
+#ifndef SAM3_MEMMAP_H
+#define SAM3_MEMMAP_H
 
 /* Peripheral and SRAM base address in the alias region */
 #define PERIPH_BB_BASE        (0x42000000)
@@ -141,4 +141,4 @@
 #define NVIC_BASE             (SCS_BASE + 0x0100)
 #define SCB_BASE              (SCS_BASE + 0x0D00)
 
-#endif /* STM32_MEMMAP_H */
+#endif /* SAM3_MEMMAP_H */

diff --git a/bertos/cpu/cortex-m3/io/sam3_pmc.h b/bertos/cpu/cortex-m3/io/sam3_pmc.h
index ea5930de3b4581895279d4af2d30bbb26976bb79..3d561a883680777825bcf08ef45c37c9ef6d2a9f 100644 (file)
--- a/bertos/cpu/cortex-m3/io/sam3_pmc.h
+++ b/bertos/cpu/cortex-m3/io/sam3_pmc.h
@@ -46,9 +46,9 @@
 #define PMC_PCER_R  (*((reg32_t *)0x400E0410))   ///< Peripheral Clock Enable Register
 #define PMC_PCDR_R  (*((reg32_t *)0x400E0414))   ///< Peripheral Clock Disable Register
 #define PMC_PCSR_R  (*((reg32_t *)0x400E0418))   ///< Peripheral Clock Status Register
-#define PMC_MOR_R   (*((reg32_t *)0x400E0420))   ///< Main Oscillator Register
-#define PMC_MCFR_R  (*((reg32_t *)0x400E0424))   ///< Main Clock Frequency Register
-#define PMC_PLLR_R  (*((reg32_t *)0x400E0428))   ///< PLL Register
+#define CKGR_MOR_R  (*((reg32_t *)0x400E0420))   ///< Main Oscillator Register
+#define CKGR_MCFR_R (*((reg32_t *)0x400E0424))   ///< Main Clock Frequency Register
+#define CKGR_PLLR_R (*((reg32_t *)0x400E0428))   ///< PLL Register
 #define PMC_MCKR_R  (*((reg32_t *)0x400E0430))   ///< Master Clock Register
 #define PMC_PCK_R   (*((reg32_t *)0x400E0440))   ///< Programmable Clock 0 Register
 #define PMC_IER_R   (*((reg32_t *)0x400E0460))   ///< Interrupt Enable Register
@@ -262,13 +262,13 @@
  */
 /*\{*/
 #define CKGR_PLLR_DIV_M           0xff   ///< Divider mask
-#define CKGR_PLLR_DIV(value)      ((CKGR_PLLR_DIV_M & (value))
+#define CKGR_PLLR_DIV(value)      (CKGR_PLLR_DIV_M & (value))
 #define CKGR_PLLR_PLLCOUNT_S      8
 #define CKGR_PLLR_PLLCOUNT_M      (0x3f << CKGR_PLLR_PLLCOUNT_S)   ///< PLL Counter mask
-#define CKGR_PLLR_PLLCOUNT(value) ((CKGR_PLLR_PLLCOUNT_M & ((value) << CKGR_PLLR_PLLCOUNT_S)))
+#define CKGR_PLLR_PLLCOUNT(value) (CKGR_PLLR_PLLCOUNT_M & ((value) << CKGR_PLLR_PLLCOUNT_S))
 #define CKGR_PLLR_MUL_S           16
 #define CKGR_PLLR_MUL_M           (0x7ff << CKGR_PLLR_MUL_S)   ///< PLL Multiplier mask
-#define CKGR_PLLR_MUL(value)      ((CKGR_PLLR_MUL_M & ((value) << CKGR_PLLR_MUL_S)))
+#define CKGR_PLLR_MUL(value)      (CKGR_PLLR_MUL_M & ((value) << CKGR_PLLR_MUL_S))
 #define CKGR_PLLR_STUCKTO1        BV(29)
 /*\}*/