Add wizard info and fix some comments.

git-svn-id: https://src.develer.com/svnoss/bertos/trunk@2292 38d2e660-2303-0410-9eaa-f027e97ec537

diff --git a/bertos/cfg/cfg_ser.h b/bertos/cfg/cfg_ser.h
index 2555626cf316d3efc33c22cd278d1a7e7a5f2f36..501d017a469b3f4de5907aae59f8bb83ed3bd7a2 100644 (file)
--- a/bertos/cfg/cfg_ser.h
+++ b/bertos/cfg/cfg_ser.h
@@ -45,87 +45,99 @@
  * spi port.
  * Edit these define for your project.
  */
- 
-/// Serial port settings
+
+/// Serial port settings. $WIZARD = { "type" : "int" }
 #define CONFIG_SER_PORT      0
-/// Serial port baudrate
+/// Serial port baudrate. $WIZARD = { "type" : "int" }
 #define CONFIG_SER_BAUDRATE  115200
 
-/// Spi port settings
+/// Spi port settings. $WIZARD = { "type" : "int" }
 #define CONFIG_SPI_PORT      0
-/// Spi port baudrate
+/// Spi port baudrate. $WIZARD = { "type" : "int" }
 #define CONFIG_SPI_BAUDRATE  5000000UL
 
 
-/// [bytes] Size of the outbound FIFO buffer for port 0.
+/// [bytes] Size of the outbound FIFO buffer for port 0. $WIZARD = { "type" : "int" }
 #define CONFIG_UART0_TXBUFSIZE  32
 
-/// [bytes] Size of the inbound FIFO buffer for port 0.
+/// [bytes] Size of the inbound FIFO buffer for port 0. $WIZARD = { "type" : "int" }
 #define CONFIG_UART0_RXBUFSIZE  32
 
-/// [bytes] Size of the outbound FIFO buffer for port 1.
+/// [bytes] Size of the outbound FIFO buffer for port 1. $WIZARD = { "type" : "int" }
 #define CONFIG_UART1_TXBUFSIZE  32
 
-/// [bytes] Size of the inbound FIFO buffer for port 1.
+/// [bytes] Size of the inbound FIFO buffer for port 1. $WIZARD = { "type" : "int" }
 #define CONFIG_UART1_RXBUFSIZE  32
 
 
-/// [bytes] Size of the outbound FIFO buffer for SPI port (AVR only)
+/// [bytes] Size of the outbound FIFO buffer for SPI port (AVR only). $WIZARD = { "type" : "int" }
 #define CONFIG_SPI_TXBUFSIZE    32
 
-/// [bytes] Size of the inbound FIFO buffer for SPI port (AVR only)
+/// [bytes] Size of the inbound FIFO buffer for SPI port (AVR only). $WIZARD = { "type" : "int" }
 #define CONFIG_SPI_RXBUFSIZE    32
 
-/// [bytes] Size of the outbound FIFO buffer for SPI port 0.
+/// [bytes] Size of the outbound FIFO buffer for SPI port 0. $WIZARD = { "type" : "int" }
 #define CONFIG_SPI0_TXBUFSIZE  32
 
-/// [bytes] Size of the inbound FIFO buffer for SPI port 0.
+/// [bytes] Size of the inbound FIFO buffer for SPI port 0. $WIZARD = { "type" : "int" }
 #define CONFIG_SPI0_RXBUFSIZE  32
 
-/// [bytes] Size of the outbound FIFO buffer for SPI port 1.
+/// [bytes] Size of the outbound FIFO buffer for SPI port 1. $WIZARD = { "type" : "int" }
 #define CONFIG_SPI1_TXBUFSIZE  32
 
-/// [bytes] Size of the inbound FIFO buffer for SPI port 1.
+/// [bytes] Size of the inbound FIFO buffer for SPI port 1. $WIZARD = { "type" : "int" }
 #define CONFIG_SPI1_RXBUFSIZE  32
 
-/// SPI data order (AVR only).
+/**
+ * SPI data order (AVR only).
+ *
+ * $WIZARD = {
+ * "type" : "enum",
+ * "value_list" : "ser_order_bit"
+ * }
+ */
 #define CONFIG_SPI_DATA_ORDER  SER_MSB_FIRST
 
-/// SPI clock division factor (AVR only).
+/// SPI clock division factor (AVR only). $WIZARD = { "type" : "int" }
 #define CONFIG_SPI_CLOCK_DIV   16
+/**
+ * SPI clock polarity: normal low or normal high (AVR only).
+ * $WIZARD = {
+ * "type" : "enum",
+ * "value_list" : "ser_spi_pol"
+ * }
+ */
+#define CONFIG_SPI_CLOCK_POL        SPI_NORMAL_LOW
 
-/// SPI clock polarity: 0 = normal low, 1 = normal high (AVR only).
-#define CONFIG_SPI_CLOCK_POL   0
-
-/// SPI clock phase: 0 = sample on first edge, 1 = sample on second clock edge (AVR only).
-#define CONFIG_SPI_CLOCK_PHASE 0
+/**
+ * SPI clock phase you can choose sample on first edge or
+ * sample on second clock edge (AVR only)
+ * $WIZARD = {
+ * "type" : "enum",
+ * "value_list" : "ser_spi_phase"
+ * }
+ */
+#define CONFIG_SPI_CLOCK_PHASE     SPI_SAMPLE_ON_FIRST_EDGE
 
-/// Default transmit timeout (ms). Set to -1 to disable timeout support.
+/// Default transmit timeout (ms). Set to -1 to disable timeout support. $WIZARD = { "type" : "int" }
 #define CONFIG_SER_TXTIMEOUT    -1
 
-/// Default receive timeout (ms). Set to -1 to disable timeout support.
+/// Default receive timeout (ms). Set to -1 to disable timeout support. $WIZARD = { "type" : "int" }
 #define CONFIG_SER_RXTIMEOUT    -1
 
-/// Use RTS/CTS handshake
+/// Use RTS/CTS handshake. $WIZARD = { "type" : "boolean" }
 #define CONFIG_SER_HWHANDSHAKE   0
 
-/// Default baud rate (set to 0 to disable).
+/// Default baud rate (set to 0 to disable). $WIZARD = { "type" : "boolean" }
 #define CONFIG_SER_DEFBAUDRATE   0
 
-/// Enable ser_gets() and ser_gets_echo().
+/// Enable ser_gets() and ser_gets_echo(). $WIZARD = { "type" : "boolean" }
 #define CONFIG_SER_GETS          0
 
-/// Enable second serial port in emulator.
+/// Enable second serial port in emulator. $WIZARD = { "type" : "boolean" }
 #define CONFIG_EMUL_UART1        0
 
-/**
- * Transmit always something on serial port 0 TX
- * to avoid interference when sending burst of data,
- * using AVR multiprocessor serial mode
- */
-#define CONFIG_SER_TXFILL        0
-
-/// For serial debug.
+/// For serial debug. $WIZARD = { "type" : "boolean" }
 #define CONFIG_SER_STROBE        0
 
 #endif /* CFG_SER_H */

diff --git a/bertos/cpu/avr/drv/ser_avr.h b/bertos/cpu/avr/drv/ser_avr.h
index 4b5518b47ea32f8fc58c38519f9b63a72e698346..237c3040d03dfacaa1ece8d8dd025626c4f488e0 100644 (file)
--- a/bertos/cpu/avr/drv/ser_avr.h
+++ b/bertos/cpu/avr/drv/ser_avr.h
@@ -60,6 +60,26 @@ typedef uint8_t serstatus_t;
 #define SERRF_NOISEERROR     0      /**< Unsupported */
 
 
+/**
+ * SPI clock polarity.
+ *
+ * $WIZARD_LIST = {
+ * "ser_spi_pol" : ["SPI_NORMAL_LOW", "SPI_NORMAL_HIGH"]
+ * }
+ */
+#define SPI_NORMAL_LOW      0
+#define SPI_NORMAL_HIGH     1
+
+/**
+ * SPI clock phase.
+ *
+ * $WIZARD_LIST = {
+ * "ser_spi_phase": ["SPI_SAMPLE_ON_FIRST_EDGE", "SPI_SAMPLE_ON_SECOND_EDGE"]
+ * }
+ */
+#define SPI_SAMPLE_ON_FIRST_EDGE    0
+#define SPI_SAMPLE_ON_SECOND_EDGE   1
+
 /**
  * \name Serial hw numbers
  *

diff --git a/bertos/drv/ser.h b/bertos/drv/ser.h
index d74c2235e94c3d70d31c9a249aad508c9c279bce..b0e0f36666778e9878c3e13ecfe04b4ece5ef1f5 100644 (file)
--- a/bertos/drv/ser.h
+++ b/bertos/drv/ser.h
@@ -35,6 +35,12 @@
  *
  * \version $Id$
  * \author Bernie Innocenti <bernie@codewiz.org>
+ *
+ * $WIZARD_MODULE = {
+ * "name" : "ser",
+ * "depends" : ["kfile", "timer"],
+ * "configuration" : "bertos/cfg/cfg_ser.h"
+ * }
  */
 
 #ifndef DRV_SER_H
@@ -92,11 +98,13 @@
 
 /**
  * \name LSB or MSB first data order for SPI driver.
- * \{
+ *
+ * $WIZARD_LIST = {
+ * "ser_order_bit" : ["SER_MSB_FIRST", "SER_LSB_FIRST"]
+ * }
  */
 #define SER_MSB_FIRST 0
 #define SER_LSB_FIRST 1
-/*\}*/
 
 /**
  * \name Parity settings for ser_setparity().