Fix some errors.

git-svn-id: https://src.develer.com/svnoss/bertos/trunk@900 38d2e660-2303-0410-9eaa-f027e97ec537

diff --git a/cpu/arm/io/at91_us.h b/cpu/arm/io/at91_us.h
index 4015ae4bb276e88fde1a5bb54ef78c233b8546bc..9b544e81b5f9dabf8fbb64c39964b13560e6b042 100644 (file)
--- a/cpu/arm/io/at91_us.h
+++ b/cpu/arm/io/at91_us.h
@@ -69,16 +69,16 @@
  * For additional information see http://www.ethernut.de/
  */
 
-#ifndef _AT91_US_H_
-#define _AT91_US_H_
+#ifndef AT91_US_H
+#define AT91_US_H
 
 /**
  * USART Control Register
  */
 /*\{*/
 #define US_CR_OFF               0x00000000      ///< USART control register offset.
-#define US0_CR  (*((reg32_t *)(USART0_BASE + US_CR_OFF)       ///< Channel 0 control register address.
-#define US1_CR  (*((reg32_t *)(USART1_BASE + US_CR_OFF)       ///< Channel 1 control register address.
+#define US0_CR  (*((reg32_t *)(USART0_BASE + US_CR_OFF)))       ///< Channel 0 control register address.
+#define US1_CR  (*((reg32_t *)(USART1_BASE + US_CR_OFF)))       ///< Channel 1 control register address.
 #define US_RSTRX                         2      ///< Reset receiver. */
 #define US_RSTTX                         3      ///< Reset transmitter.
 #define US_RXEN                          4      ///< Receiver enable.
@@ -104,8 +104,8 @@
  */
 /*\{*/
 #define US_MR_OFF               0x00000004      ///< USART mode register offset.
-#define US0_MR  (*((reg32_t *)(USART0_BASE + US_MR_OFF)       ///< Channel 0 mode register address.
-#define US1_MR  (*((reg32_t *)(USART1_BASE + US_MR_OFF)       ///< Channel 1 mode register address.
+#define US0_MR  (*((reg32_t *)(USART0_BASE + US_MR_OFF)))       ///< Channel 0 mode register address.
+#define US1_MR  (*((reg32_t *)(USART1_BASE + US_MR_OFF)))       ///< Channel 1 mode register address.
 
 #define US_USART_MODE_MASK      0x0000000F      ///< USART mode mask.
 #define US_USART_MODE_NORMA     0x00000000      ///< Normal.
@@ -167,20 +167,20 @@
  */
 /*\{*/
 #define US_IER_OFF              0x00000008      ///< USART interrupt enable register offset.
-#define US0_IER (*((reg32_t *)(USART0_BASE + US_IER_OFF)      ///< Channel 0 interrupt enable register address.
-#define US1_IER (*((reg32_t *)(USART1_BASE + US_IER_OFF)      ///< Channel 1 interrupt enable register address.
+#define US0_IER (*((reg32_t *)(USART0_BASE + US_IER_OFF)))      ///< Channel 0 interrupt enable register address.
+#define US1_IER (*((reg32_t *)(USART1_BASE + US_IER_OFF)))      ///< Channel 1 interrupt enable register address.
 
 #define US_IDR_OFF              0x0000000C      ///< USART interrupt disable register offset.
-#define US0_IDR (*((reg32_t *)(USART0_BASE + US_IDR_OFF)      ///< Channel 0 interrupt disable register address.
-#define US1_IDR (*((reg32_t *)(USART1_BASE + US_IDR_OFF)      ///< Channel 1 interrupt disable register address.
+#define US0_IDR (*((reg32_t *)(USART0_BASE + US_IDR_OFF)))      ///< Channel 0 interrupt disable register address.
+#define US1_IDR (*((reg32_t *)(USART1_BASE + US_IDR_OFF)))      ///< Channel 1 interrupt disable register address.
 
 #define US_IMR_OFF              0x00000010      ///< USART interrupt mask register offset.
-#define US0_IMR (*((reg32_t *)(USART0_BASE + US_IMR_OFF)      ///< Channel 0 interrupt mask register address.
-#define US1_IMR (*((reg32_t *)(USART1_BASE + US_IMR_OFF)      ///< Channel 1 interrupt mask register address.
+#define US0_IMR (*((reg32_t *)(USART0_BASE + US_IMR_OFF)))      ///< Channel 0 interrupt mask register address.
+#define US1_IMR (*((reg32_t *)(USART1_BASE + US_IMR_OFF)))      ///< Channel 1 interrupt mask register address.
 
 #define US_CSR_OFF              0x00000014      ///< USART status register offset.
-#define US0_CSR (*((reg32_t *)(USART0_BASE + US_CSR_OFF)      ///< Channel 0 status register address.
-#define US1_CSR (*((reg32_t *)(USART1_BASE + US_CSR_OFF)      ///< Channel 1 status register address.
+#define US0_CSR (*((reg32_t *)(USART0_BASE + US_CSR_OFF)))      ///< Channel 0 status register address.
+#define US1_CSR (*((reg32_t *)(USART1_BASE + US_CSR_OFF)))      ///< Channel 1 status register address.
 #define US_CSR_RI                       20      ///< Image of RI input.
 #define US_CSR_DSR                      21      ///< Image of DSR input.
 #define US_CSR_DCD                      22      ///< Image of DCD input.
@@ -210,8 +210,8 @@
  */
 /*\{*/
 #define US_RHR_OFF              0x00000018      ///< USART receiver holding register offset.
-#define US0_RHR (*((reg32_t *)(USART0_BASE + US_RHR_OFF)      ///< Channel 0 receiver holding register address.
-#define US1_RHR (*((reg32_t *)(USART1_BASE + US_RHR_OFF)      ///< Channel 1 receiver holding register address.
+#define US0_RHR (*((reg32_t *)(USART0_BASE + US_RHR_OFF)))      ///< Channel 0 receiver holding register address.
+#define US1_RHR (*((reg32_t *)(USART1_BASE + US_RHR_OFF)))      ///< Channel 1 receiver holding register address.
 #define US_RHR_RXCHR_MASK       0x000001FF      ///< Last char received if US_RXRDY is set.
 #define US_RHR_RXSYNH                   15      ///< Received sync.
 /*\}*/
@@ -221,8 +221,8 @@
  */
 /*\{*/
 #define US_THR_OFF              0x0000001C      ///< USART transmitter holding register offset.
-#define US0_THR (*((reg32_t *)(USART0_BASE + US_THR_OFF)      ///< Channel 0 transmitter holding register address.
-#define US1_THR (*((reg32_t *)(USART1_BASE + US_THR_OFF)      ///< Channel 1 transmitter holding register address.
+#define US0_THR (*((reg32_t *)(USART0_BASE + US_THR_OFF)))      ///< Channel 0 transmitter holding register address.
+#define US1_THR (*((reg32_t *)(USART1_BASE + US_THR_OFF)))      ///< Channel 1 transmitter holding register address.
 #define US_THR_TXCHR_MASK       0x000001FF      ///< Next char to be trasmitted.
 #define US_THR_TXSYNH                   15      ///< Sync field to be trasmitted.
 /*\}*/
@@ -232,8 +232,8 @@
  */
 /*\{*/
 #define US_BRGR_OFF             0x00000020      ///< USART baud rate register offset.
-#define US0_BRGR (*((reg32_t *)(USART0_BASE + US_BRGR_OFF)    ///< Channel 0 baud rate register address.
-#define US1_BRGR (*((reg32_t *)(USART1_BASE + US_BRGR_OFF)    ///< Channel 1 baud rate register address.
+#define US0_BRGR (*((reg32_t *)(USART0_BASE + US_BRGR_OFF)))    ///< Channel 0 baud rate register address.
+#define US1_BRGR (*((reg32_t *)(USART1_BASE + US_BRGR_OFF)))    ///< Channel 1 baud rate register address.
 #define US_BRGR_MASK            0x0000FFFF      ///< Clock divider.
 #define US_BRGR_FP_MASK         0x001F0000      ///< Fractional part.
 /*\}*/
@@ -243,8 +243,8 @@
  */
 /*\{*/
 #define US_RTOR_OFF             0x00000024      ///< USART receiver timeout register offset.
-#define US0_RTOR (*((reg32_t *)(USART0_BASE + US_RTOR_OFF)    ///< Channel 0 receiver timeout register address.
-#define US1_RTOR (*((reg32_t *)(USART1_BASE + US_RTOR_OFF)    ///< Channel 1 receiver timeout register address.
+#define US0_RTOR (*((reg32_t *)(USART0_BASE + US_RTOR_OFF)))    ///< Channel 0 receiver timeout register address.
+#define US1_RTOR (*((reg32_t *)(USART1_BASE + US_RTOR_OFF)))    ///< Channel 1 receiver timeout register address.
 /*\}*/
 
 /**
@@ -252,8 +252,8 @@
  */
 /*\{*/
 #define US_TTGR_OFF             0x00000028      ///< USART transmitter time guard register offset.
-#define US0_TTGR (*((reg32_t *)(USART0_BASE + US_TTGR_OFF)    ///< Channel 0 transmitter time guard register address.
-#define US1_TTGR (*((reg32_t *)(USART1_BASE + US_TTGR_OFF)    ///< Channel 1 transmitter time guard register address.
+#define US0_TTGR (*((reg32_t *)(USART0_BASE + US_TTGR_OFF)))    ///< Channel 0 transmitter time guard register address.
+#define US1_TTGR (*((reg32_t *)(USART1_BASE + US_TTGR_OFF)))    ///< Channel 1 transmitter time guard register address.
 /*\}*/
 
 /**
@@ -261,8 +261,8 @@
 */
 /*\{*/
 #define US_FIDI_OFF             0x00000040      ///< USART FI DI ratio register offset.
-#define US0_FIDI (*((reg32_t *)(USART0_BASE + US_FIDI_OFF)    ///< Channel 0 FI DI ratio register address.
-#define US1_FIDI (*((reg32_t *)(USART1_BASE + US_FIDI_OFF)    ///< Channel 1 FI DI ratio register address.
+#define US0_FIDI (*((reg32_t *)(USART0_BASE + US_FIDI_OFF)))    ///< Channel 0 FI DI ratio register address.
+#define US1_FIDI (*((reg32_t *)(USART1_BASE + US_FIDI_OFF)))    ///< Channel 1 FI DI ratio register address.
 /*\}*/
 
 /**
@@ -270,8 +270,8 @@
  */
 /*\{*/
 #define US_NER_OFF              0x00000044      ///< USART error counter register offset.
-#define US0_NER  (*((reg32_t *)(USART0_BASE + US_NER_OFF)     ///< Channel 0 error counter register address.
-#define US1_NER  (*((reg32_t *)(USART1_BASE + US_NER_OFF)     ///< Channel 1 error counter register address.
+#define US0_NER  (*((reg32_t *)(USART0_BASE + US_NER_OFF)))     ///< Channel 0 error counter register address.
+#define US1_NER  (*((reg32_t *)(USART1_BASE + US_NER_OFF)))     ///< Channel 1 error counter register address.
 /*\}*/
 
 /**
@@ -279,70 +279,69 @@
  */
 /*\{*/
 #define US_IF_OFF               0x0000004C      ///< USART IrDA filter register offset.
-#define US0_IF (*((reg32_t *)(USART0_BASE + US_IF_OFF)        ///< Channel 0 IrDA filter register address.
-#define US1_IF (*((reg32_t *)(USART1_BASE + US_IF_OFF)        ///< Channel 1 IrDA filter register address.
+#define US0_IF (*((reg32_t *)(USART0_BASE + US_IF_OFF)))        ///< Channel 0 IrDA filter register address.
+#define US1_IF (*((reg32_t *)(USART1_BASE + US_IF_OFF)))        ///< Channel 1 IrDA filter register address.
 /*\}*/
 
-#if defined(*((reg32_t *)(USART_HAS_PDC)
-
-/**
- * Receive Pointer Register
- */
-/*\{*/
-#define US0_RPR (*((reg32_t *)(USART0_BASE + PERIPH_RPR_OFF)      ///< Channel 0 receive pointer register address.
-#define US1_RPR (*((reg32_t *)(USART1_BASE + PERIPH_RPR_OFF)      ///< Channel 1 receive pointer register address.
-/*\}*/
-
-/**
- * Receive Counter Register
- */
-/*\{*/
-#define US0_RCR (*((reg32_t *)(USART0_BASE + PERIPH_RCR_OFF)      ///< Channel 0 receive counter register address.
-#define US1_RCR (*((reg32_t *)(USART1_BASE + PERIPH_RCR_OFF)      ///< Channel 1 receive counter register address.
-/*\}*/
-
-/**
- * Transmit Pointer Register
- */
-/*\{*/
-#define US0_TPR (*((reg32_t *)(USART0_BASE + PERIPH_TPR_OFF)      ///< Channel 0 transmit pointer register address.
-#define US1_TPR (*((reg32_t *)(USART1_BASE + PERIPH_TPR_OFF)      ///< Channel 1 transmit pointer register address.
-/*\}*/
-
-/**
- * Name Transmit Counter Register
- */
-/*\{*/
-#define US0_TCR (*((reg32_t *)(USART0_BASE + PERIPH_TCR_OFF)      ///< Channel 0 transmit counter register address.
-#define US1_TCR (*((reg32_t *)(USART1_BASE + PERIPH_TCR_OFF)      ///< Channel 1 transmit counter register address.
-/*\}*/
-
-#if defined(PERIPH_RNPR_OFF) && defined(PERIPH_RNCR_OFF)
-#define US0_RNPR   (*((reg32_t *)(USART0_BASE + PERIPH_RNPR_OFF)  ///< PDC channel 0 receive next pointer register.
-#define US1_RNPR   (*((reg32_t *)(USART1_BASE + PERIPH_RNPR_OFF)  ///< PDC channel 1 receive next pointer register.
-#define US0_RNCR   (*((reg32_t *)(USART0_BASE + PERIPH_RNCR_OFF)  ///< PDC channel 0 receive next counter register.
-#define US1_RNCR   (*((reg32_t *)(USART1_BASE + PERIPH_RNCR_OFF)  ///< PDC channel 1 receive next counter register.
-#endif
-
-#if defined(PERIPH_TNPR_OFF) && defined(PERIPH_TNCR_OFF)
-#define US0_TNPR   (*((reg32_t *)(USART0_BASE + PERIPH_TNPR_OFF)  ///< PDC channel 0 transmit next pointer register.
-#define US1_TNPR   (*((reg32_t *)(USART1_BASE + PERIPH_TNPR_OFF)  ///< PDC channel 1 transmit next pointer register.
-#define US0_TNCR   (*((reg32_t *)(USART0_BASE + PERIPH_TNCR_OFF)  ///< PDC channel 0 transmit next counter register.
-#define US1_TNCR   (*((reg32_t *)(USART1_BASE + PERIPH_TNCR_OFF)  ///< PDC channel 1 transmit next counter register.
-#endif
-
-#if defined(PERIPH_PTCR_OFF)
-#define US0_PTCR   (*((reg32_t *)(USART0_BASE + PERIPH_PTCR_OFF)  ///< PDC channel 0 transfer control register.
-#define US1_PTCR   (*((reg32_t *)(USART1_BASE + PERIPH_PTCR_OFF)  ///< PDC channel 1 transfer control register.
-#endif
-
-#if defined(PERIPH_PTSR_OFF)
-#define US0_PTSR   (*((reg32_t *)(USART0_BASE + PERIPH_PTSR_OFF)  ///< PDC channel 0 transfer status register.
-#define US1_PTSR   (*((reg32_t *)(USART1_BASE + PERIPH_PTSR_OFF)  ///< PDC channel 1 transfer status register.
-#endif
+#if USART_HAS_PDC
+
+       /**
+       * Receive Pointer Register
+       */
+       /*\{*/
+       #define US0_RPR (*((reg32_t *)(USART0_BASE + PERIPH_RPR_OFF)))      ///< Channel 0 receive pointer register address.
+       #define US1_RPR (*((reg32_t *)(USART1_BASE + PERIPH_RPR_OFF)))      ///< Channel 1 receive pointer register address.
+       /*\}*/
+
+       /**
+       * Receive Counter Register
+       */
+       /*\{*/
+       #define US0_RCR (*((reg32_t *)(USART0_BASE + PERIPH_RCR_OFF)))      ///< Channel 0 receive counter register address.
+       #define US1_RCR (*((reg32_t *)(USART1_BASE + PERIPH_RCR_OFF)))      ///< Channel 1 receive counter register address.
+       /*\}*/
+
+       /**
+       * Transmit Pointer Register
+       */
+       /*\{*/
+       #define US0_TPR (*((reg32_t *)(USART0_BASE + PERIPH_TPR_OFF)))      ///< Channel 0 transmit pointer register address.
+       #define US1_TPR (*((reg32_t *)(USART1_BASE + PERIPH_TPR_OFF)))      ///< Channel 1 transmit pointer register address.
+       /*\}*/
+
+       /**
+       * Transmit Counter Register
+       */
+       /*\{*/
+       #define US0_TCR (*((reg32_t *)(USART0_BASE + PERIPH_TCR_OFF)))      ///< Channel 0 transmit counter register address.
+       #define US1_TCR (*((reg32_t *)(USART1_BASE + PERIPH_TCR_OFF)))      ///< Channel 1 transmit counter register address.
+       /*\}*/
+
+       #if defined(PERIPH_RNPR_OFF) && defined(PERIPH_RNCR_OFF)
+       #define US0_RNPR   (*((reg32_t *)(USART0_BASE + PERIPH_RNPR_OFF)))  ///< PDC channel 0 receive next pointer register.
+       #define US1_RNPR   (*((reg32_t *)(USART1_BASE + PERIPH_RNPR_OFF)))  ///< PDC channel 1 receive next pointer register.
+       #define US0_RNCR   (*((reg32_t *)(USART0_BASE + PERIPH_RNCR_OFF)))  ///< PDC channel 0 receive next counter register.
+       #define US1_RNCR   (*((reg32_t *)(USART1_BASE + PERIPH_RNCR_OFF)))  ///< PDC channel 1 receive next counter register.
+       #endif
+
+       #if defined(PERIPH_TNPR_OFF) && defined(PERIPH_TNCR_OFF)
+       #define US0_TNPR   (*((reg32_t *)(USART0_BASE + PERIPH_TNPR_OFF)))  ///< PDC channel 0 transmit next pointer register.
+       #define US1_TNPR   (*((reg32_t *)(USART1_BASE + PERIPH_TNPR_OFF)))  ///< PDC channel 1 transmit next pointer register.
+       #define US0_TNCR   (*((reg32_t *)(USART0_BASE + PERIPH_TNCR_OFF)))  ///< PDC channel 0 transmit next counter register.
+       #define US1_TNCR   (*((reg32_t *)(USART1_BASE + PERIPH_TNCR_OFF)))  ///< PDC channel 1 transmit next counter register.
+       #endif
+
+       #if defined(PERIPH_PTCR_OFF)
+       #define US0_PTCR   (*((reg32_t *)(USART0_BASE + PERIPH_PTCR_OFF)))  ///< PDC channel 0 transfer control register.
+       #define US1_PTCR   (*((reg32_t *)(USART1_BASE + PERIPH_PTCR_OFF)))  ///< PDC channel 1 transfer control register.
+       #endif
+
+       #if defined(PERIPH_PTSR_OFF)
+       #define US0_PTSR   (*((reg32_t *)(USART0_BASE + PERIPH_PTSR_OFF)))  ///< PDC channel 0 transfer status register.
+       #define US1_PTSR   (*((reg32_t *)(USART1_BASE + PERIPH_PTSR_OFF)))  ///< PDC channel 1 transfer status register.
+       #endif
 
 #endif  /* USART_HAS_PDC */
 
 
-#endif                          /* _AT91_US_H_ */
-
+#endif /* AT91_US_H */