Deleted deprecated crt.s

git-svn-id: https://src.develer.com/svnoss/bertos/trunk@1473 38d2e660-2303-0410-9eaa-f027e97ec537

diff --git a/bertos/cpu/arm/hw/crt.s b/bertos/cpu/arm/hw/crt.s
deleted file mode 100644 (file)
index 98d723e..0000000
--- a/bertos/cpu/arm/hw/crt.s
+++ /dev/null
@@ -1,223 +0,0 @@
-/****************************************************************************\r
-*  Copyright (c) 2006 by Michael Fischer. All rights reserved.\r
-*\r
-*  Redistribution and use in source and binary forms, with or without \r
-*  modification, are permitted provided that the following conditions \r
-*  are met:\r
-*  \r
-*  1. Redistributions of source code must retain the above copyright \r
-*     notice, this list of conditions and the following disclaimer.\r
-*  2. Redistributions in binary form must reproduce the above copyright\r
-*     notice, this list of conditions and the following disclaimer in the \r
-*     documentation and/or other materials provided with the distribution.\r
-*  3. Neither the name of the author nor the names of its contributors may \r
-*     be used to endorse or promote products derived from this software \r
-*     without specific prior written permission.\r
-*\r
-*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \r
-*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT \r
-*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS \r
-*  FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL \r
-*  THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, \r
-*  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, \r
-*  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS \r
-*  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED \r
-*  AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, \r
-*  OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF \r
-*  THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF \r
-*  SUCH DAMAGE.\r
-*\r
-****************************************************************************\r
-*\r
-*  History:\r
-*\r
-*  18.12.06  mifi   First Version\r
-*                   The hardware initialization is based on the startup file\r
-*                   crtat91sam7x256_rom.S from NutOS 4.2.1. \r
-*                   Therefore partial copyright by egnite Software GmbH.\r
-****************************************************************************/\r
-\r
-/*\r
- * Some defines for the program status registers\r
- */\r
-   ARM_MODE_USER  = 0x10      /* Normal User Mode                             */ \r
-   ARM_MODE_FIQ   = 0x11      /* FIQ Fast Interrupts Mode                     */\r
-   ARM_MODE_IRQ   = 0x12      /* IRQ Standard Interrupts Mode                 */\r
-   ARM_MODE_SVC   = 0x13      /* Supervisor Interrupts Mode                   */\r
-   ARM_MODE_ABORT = 0x17      /* Abort Processing memory Faults Mode          */\r
-   ARM_MODE_UNDEF = 0x1B      /* Undefined Instructions Mode                  */\r
-   ARM_MODE_SYS   = 0x1F      /* System Running in Priviledged Operating Mode */\r
-   ARM_MODE_MASK  = 0x1F\r
-   \r
-   I_BIT          = 0x80      /* disable IRQ when I bit is set */\r
-   F_BIT          = 0x40      /* disable IRQ when I bit is set */\r
-   \r
-/*\r
- * Register Base Address\r
- */\r
-   AIC_BASE         = 0xFFFFF000\r
-   AIC_EOICR_OFF    = 0x130\r
-   AIC_IDCR_OFF     = 0x124\r
-\r
-   RSTC_MR          = 0xFFFFFD08\r
-   RSTC_KEY         = 0xA5000000\r
-   RSTC_URSTEN      = 0x00000001\r
-\r
-   WDT_BASE         = 0xFFFFFD40\r
-   WDT_MR_OFF       = 0x00000004\r
-   WDT_WDDIS        = 0x00008000\r
-\r
-   MC_BASE          = 0xFFFFFF00\r
-   MC_FMR_OFF       = 0x00000060\r
-   MC_FWS_1FWS      = 0x00480100\r
-      \r
-   .section .vectors,"ax"\r
-   .code 32\r
-        \r
-/****************************************************************************/\r
-/*               Vector table and reset entry                               */\r
-/****************************************************************************/\r
-_vectors:\r
-   ldr pc, ResetAddr     /* Reset                 */\r
-   ldr pc, UndefAddr     /* Undefined instruction */\r
-   ldr pc, SWIAddr       /* Software interrupt    */\r
-   ldr pc, PAbortAddr    /* Prefetch abort        */\r
-   ldr pc, DAbortAddr    /* Data abort            */\r
-   ldr pc, ReservedAddr  /* Reserved              */\r
-   ldr pc, [pc, #-0xF20] /* IRQ interrupt         */\r
-   ldr pc, FIQAddr       /* FIQ interrupt         */\r
-\r
-.extern maion\r
-\r
-ResetAddr:     .word ResetHandler\r
-UndefAddr:     .word UndefHandler\r
-SWIAddr:       .word SWIHandler\r
-PAbortAddr:    .word PAbortHandler\r
-DAbortAddr:    .word DAbortHandler\r
-ReservedAddr:  .word 0\r
-IRQAddr:       .word IRQHandler\r
-FIQAddr:       .word FIQHandler\r
-\r
-   .ltorg\r
-\r
-   .section .init, "ax"\r
-   .code 32\r
-   \r
-   .global ResetHandler\r
-   .global ExitFunction\r
-   .extern main\r
-/****************************************************************************/\r
-/*                           Reset handler                                  */\r
-/****************************************************************************/\r
-ResetHandler:\r
-   /*\r
-    * The watchdog is enabled after processor reset. Disable it.\r
-    */\r
-   ldr   r1, =WDT_BASE\r
-   ldr   r0, =WDT_WDDIS\r
-   str   r0, [r1, #WDT_MR_OFF]\r
-\r
-   \r
-   /*\r
-    * Enable user reset: assertion length programmed to 1ms\r
-    */\r
-   ldr   r0, =(RSTC_KEY | RSTC_URSTEN | (4 << 8))\r
-   ldr   r1, =RSTC_MR\r
-   str   r0, [r1, #0]\r
-\r
-   \r
-   /*\r
-    * Use 2 cycles for flash access.\r
-    */\r
-   ldr   r1, =MC_BASE\r
-   ldr   r0, =MC_FWS_1FWS\r
-   str   r0, [r1, #MC_FMR_OFF]\r
-\r
-\r
-   /*\r
-    * Disable all interrupts. Useful for debugging w/o target reset.\r
-    */\r
-   ldr   r1, =AIC_BASE\r
-   mvn   r0, #0\r
-   str   r0, [r1, #AIC_EOICR_OFF]\r
-   str   r0, [r1, #AIC_IDCR_OFF]\r
-\r
-    \r
-   /*\r
-    * Setup a stack for each mode\r
-    */    \r
-   msr   CPSR_c, #ARM_MODE_UNDEF | I_BIT | F_BIT   /* Undefined Instruction Mode */     \r
-   ldr   sp, =__stack_und_end\r
-   \r
-   msr   CPSR_c, #ARM_MODE_ABORT | I_BIT | F_BIT   /* Abort Mode */\r
-   ldr   sp, =__stack_abt_end\r
-   \r
-   msr   CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT     /* FIQ Mode */   \r
-   ldr   sp, =__stack_fiq_end\r
-   \r
-   msr   CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT     /* IRQ Mode */   \r
-   ldr   sp, =__stack_irq_end\r
-   \r
-   msr   CPSR_c, #ARM_MODE_SVC | I_BIT | F_BIT     /* Supervisor Mode */\r
-   ldr   sp, =__stack_svc_end\r
-\r
-\r
-   /*\r
-    * Clear .bss section\r
-    */\r
-   ldr   r1, =__bss_start\r
-   ldr   r2, =__bss_end\r
-   ldr   r3, =0\r
-bss_clear_loop:\r
-   cmp   r1, r2\r
-   strne r3, [r1], #+4\r
-   bne   bss_clear_loop\r
-   \r
-   \r
-   /*\r
-    * Jump to main\r
-    */\r
-\r
-   mov   r0, #0 /* No arguments */\r
-   mov   r1, #0 /* No arguments */\r
-   ldr   r2, =main\r
-   mov   lr, pc\r
-   bx    r2     /* And jump... */\r
-                       \r
-ExitFunction:\r
-   nop\r
-   nop\r
-   nop\r
-   b ExitFunction   \r
-   \r
-\r
-/****************************************************************************/\r
-/*                         Default interrupt handler                        */\r
-/****************************************************************************/\r
-\r
-UndefHandler:\r
-   b UndefHandler\r
-   \r
-SWIHandler:\r
-   b SWIHandler\r
-\r
-PAbortHandler:\r
-   b PAbortHandler\r
-\r
-DAbortHandler:\r
-   b DAbortHandler\r
-   \r
-IRQHandler:\r
-   b IRQHandler\r
-   \r
-FIQHandler:\r
-   b FIQHandler\r
-   \r
-   .weak ExitFunction\r
-   .weak UndefHandler, PAbortHandler, DAbortHandler\r
-   .weak IRQHandler, FIQHandler\r
-\r
-   .ltorg\r
-/*** EOF ***/   \r
-  \r
-\r