*/
#define ETH_LOG_FORMAT LOG_FMT_TERSE
+/**
+ * Select the supported phy chip.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "phy_chip_list"
+ */
+#define CONFIG_PHY_CHIP DAVICOM_DM9161A
+
+
#endif /* CFG_ETH_H */
*
* \return Contents of the specified register.
*/
-static uint16_t phy_hw_read(reg8_t reg)
+static uint16_t phy_hw_read(uint8_t reg)
{
// PHY read command.
EMAC_MAN = EMAC_SOF | EMAC_RW_READ | (NIC_PHY_ADDR << EMAC_PHYA_SHIFT)
* \param reg PHY register number.
* \param val Value to write.
*/
-static void phy_hw_write(reg8_t reg, uint16_t val)
+static void phy_hw_write(uint8_t reg, uint16_t val)
{
// PHY write command.
EMAC_MAN = EMAC_SOF | EMAC_RW_WRITE | (NIC_PHY_ADDR << EMAC_PHYA_SHIFT)
cpu_relax();
}
-static int emac_reset(void)
+INLINE void phy_manageEnable(bool en)
{
- uint16_t phy_cr;
-
- // Enable devices
- PMC_PCER = BV(PIOA_ID);
- PMC_PCER = BV(PIOB_ID);
- PMC_PCER = BV(EMAC_ID);
-
- // Disable RMII and TESTMODE by disabling pull-ups.
- PIOB_PUDR = BV(PHY_COL_RMII_BIT) | BV(PHY_RXDV_TESTMODE_BIT);
-
- // Disable PHY power down.
- PIOB_PER = BV(PHY_PWRDN_BIT);
- PIOB_OER = BV(PHY_PWRDN_BIT);
- PIOB_CODR = BV(PHY_PWRDN_BIT);
+ if (en)
+ {
+ /* Enable management port. */
+ EMAC_NCR |= BV(EMAC_MPE);
+ EMAC_NCFGR |= EMAC_CLK_HCLK_32;
+ }
+ else
+ {
+ /* Disable management port */
+ EMAC_NCR &= ~BV(EMAC_MPE);
+ }
+}
- // Toggle external hardware reset pin.
+INLINE void phy_resetPulse(void)
+{
+ /* Toggle external hardware reset pin. */
RSTC_MR = RSTC_KEY | (1 << RSTC_ERSTL_SHIFT) | BV(RSTC_URSTEN);
RSTC_CR = RSTC_KEY | BV(RSTC_EXTRST);
while ((RSTC_SR & BV(RSTC_NRSTL)) == 0)
cpu_relax();
+}
+
+INLINE void phy_pinThreeState(void)
+{
+ PIOB_PUDR = PHY_MII_PINS;
+ PIOB_ODR = PHY_MII_PINS;
+ PIOB_PER = PHY_MII_PINS;
+}
- // Configure MII port.
+INLINE void phy_pinGpio(void)
+{
+ PIOB_PUDR = PHY_MII_PINS;
+ PIOB_OWER = PHY_MII_PINS;
+ PIOB_OER = PHY_MII_PINS;
+ PIOB_PER = PHY_MII_PINS;
+}
+
+INLINE void phy_pinMac(void)
+{
+ PIOB_ODR = PHY_MII_PINS;
+ PIOB_OWDR = PHY_MII_PINS;
PIOB_ASR = PHY_MII_PINS;
PIOB_BSR = 0;
+ PIOB_PUDR = PHY_MII_PINS;
PIOB_PDR = PHY_MII_PINS;
+}
- // Enable receive and transmit clocks.
- EMAC_USRIO = BV(EMAC_CLKEN);
+INLINE void phy_pinSet(uint32_t state)
+{
+ PIOB_ODSR = state;
+}
+
+#define AUTONEGOTIATION_TIMEOUT 5000
+
+static void emac_reset(void)
+{
+ /* Enable devices */
+ PMC_PCER = BV(EMAC_ID);
- // Enable management port.
- EMAC_NCR |= BV(EMAC_MPE);
- EMAC_NCFGR |= EMAC_CLK_HCLK_32;
+ /* Enable receive and transmit clocks. */
+ EMAC_USRIO = BV(EMAC_CLKEN);
- // Set local MAC address.
+ /* Set local MAC address. */
EMAC_SA1L = (mac_addr[3] << 24) | (mac_addr[2] << 16) |
(mac_addr[1] << 8) | mac_addr[0];
EMAC_SA1H = (mac_addr[5] << 8) | mac_addr[4];
+ phy_manageEnable(true);
- // Wait for PHY ready
- timer_delay(255);
+ PHY_HW_INIT();
- // Clear MII isolate.
- phy_hw_read(NIC_PHY_BMCR);
- phy_cr = phy_hw_read(NIC_PHY_BMCR);
+ PHY_INIT();
+ phy_pinMac();
+
+ /* Clear MII isolate. */
+ uint16_t phy_cr = phy_hw_read(NIC_PHY_BMCR);
phy_cr &= ~NIC_PHY_BMCR_ISOLATE;
phy_hw_write(NIC_PHY_BMCR, phy_cr);
- phy_cr = phy_hw_read(NIC_PHY_BMCR);
-
- LOG_INFO("%s: PHY ID %#04x %#04x\n",
- __func__,
- phy_hw_read(NIC_PHY_ID1), phy_hw_read(NIC_PHY_ID2));
+ uint32_t phy_id = phy_hw_read(NIC_PHY_ID1) << 16
+ | phy_hw_read(NIC_PHY_ID2);
+ ASSERT((phy_id & 0xFFFFFFF0) == (NIC_PHY_ID & 0xFFFFFFF0));
+ LOG_INFO("PHY ID %#08lx\n", phy_id);
- // Wait for auto negotiation completed.
- phy_hw_read(NIC_PHY_BMSR);
- for (;;)
+ ticks_t start = timer_clock();
+ /* Wait for auto negotiation completed. */
+ while (1)
{
if (phy_hw_read(NIC_PHY_BMSR) & NIC_PHY_BMSR_ANCOMPL)
break;
cpu_relax();
+ if (timer_clock() - start > ms_to_ticks(AUTONEGOTIATION_TIMEOUT))
+ {
+ LOG_ERR("Autonegotiation timeout\n");
+ break;
+ }
}
-
- // Disable management port.
- EMAC_NCR &= ~BV(EMAC_MPE);
-
- return 0;
}
-static int emac_start(void)
+static void emac_start(void)
{
uint32_t addr;
int i;
/* Enable receiver, transmitter and statistics. */
EMAC_NCR |= BV(EMAC_TE) | BV(EMAC_RE) | BV(EMAC_WESTAT);
-
- return 0;
}
ssize_t eth_putFrame(const uint8_t *buf, size_t len)
#ifndef ETH_AT91_H
#define ETH_AT91_H
-// Settings and definition for DAVICOM 9161A
+// Settings and definition for PHY registers
// \{
-#define NIC_PHY_ADDR 31
//Registry definition
#define NIC_PHY_BMCR 0x00 // Basic mode control register.
#define NIC_PHY_ANLPAR 0x05 // Auto negotiation link partner availability register.
#define NIC_PHY_ANER 0x06 // Auto negotiation expansion register.
-// Pin definition for DAVICOM 9161A
-// See schematic for at91sam7x-ek evalution board
-#define PHY_TXCLK_ISOLATE_BIT 0
-#define PHY_REFCLK_XT2_BIT 0
-#define PHY_TXEN_BIT 1
-#define PHY_TXD0_BIT 2
-#define PHY_TXD1_BIT 3
-#define PHY_CRS_AD4_BIT 4
-#define PHY_RXD0_AD0_BIT 5
-#define PHY_RXD1_AD1_BIT 6
-#define PHY_RXER_RXD4_RPTR_BIT 7
-#define PHY_MDC_BIT 8
-#define PHY_MDIO_BIT 9
-#define PHY_TXD2_BIT 10
-#define PHY_TXD3_BIT 11
-#define PHY_TXER_TXD4_BIT 12
-#define PHY_RXD2_AD2_BIT 13
-#define PHY_RXD3_AD3_BIT 14
-#define PHY_RXDV_TESTMODE_BIT 15
-#define PHY_COL_RMII_BIT 16
-#define PHY_RXCLK_10BTSER_BIT 17
-#define PHY_PWRDN_BIT 18
-#define PHY_MDINTR_BIT 26
-
-#define PHY_MII_PINS BV(PHY_REFCLK_XT2_BIT) \
- | BV(PHY_TXEN_BIT) \
- | BV(PHY_TXD0_BIT) \
- | BV(PHY_TXD1_BIT) \
- | BV(PHY_CRS_AD4_BIT) \
- | BV(PHY_RXD0_AD0_BIT) \
- | BV(PHY_RXD1_AD1_BIT) \
- | BV(PHY_RXER_RXD4_RPTR_BIT) \
- | BV(PHY_MDC_BIT) \
- | BV(PHY_MDIO_BIT) \
- | BV(PHY_TXD2_BIT) \
- | BV(PHY_TXD3_BIT) \
- | BV(PHY_TXER_TXD4_BIT) \
- | BV(PHY_RXD2_AD2_BIT) \
- | BV(PHY_RXD3_AD3_BIT) \
- | BV(PHY_RXDV_TESTMODE_BIT) \
- | BV(PHY_COL_RMII_BIT) \
- | BV(PHY_RXCLK_10BTSER_BIT)
+/* Pin definition MII/RMII PHY interdace */
+#define PHY_TXCLK_BIT BV(0)
+#define PHY_TXEN_BIT BV(1)
+#define PHY_TXD0_BIT BV(2)
+#define PHY_TXD1_BIT BV(3)
+#define PHY_CRS_BIT BV(4)
+#define PHY_RXD0_BIT BV(5)
+#define PHY_RXD1_BIT BV(6)
+#define PHY_RXER_BIT BV(7)
+#define PHY_MDC_BIT BV(8)
+#define PHY_MDIO_BIT BV(9)
+#define PHY_TXD2_BIT BV(10)
+#define PHY_TXD3_BIT BV(11)
+#define PHY_TXER_BIT BV(12)
+#define PHY_RXD2_BIT BV(13)
+#define PHY_RXD3_BIT BV(14)
+#define PHY_RXDV_BIT BV(15)
+#define PHY_COL_BIT BV(16)
+#define PHY_RXCLK_BIT BV(17)
+
+#define PHY_MII_PINS \
+ ( PHY_TXEN_BIT \
+ | PHY_TXD0_BIT \
+ | PHY_TXD1_BIT \
+ | PHY_CRS_BIT \
+ | PHY_RXD0_BIT \
+ | PHY_RXD1_BIT \
+ | PHY_RXER_BIT \
+ | PHY_MDC_BIT \
+ | PHY_MDIO_BIT \
+ | PHY_TXD2_BIT \
+ | PHY_TXD3_BIT \
+ | PHY_TXER_BIT \
+ | PHY_RXD2_BIT \
+ | PHY_RXD3_BIT \
+ | PHY_RXDV_BIT \
+ | PHY_COL_BIT \
+ | PHY_RXCLK_BIT)
// \}
#define EMAC_TX_BUFSIZ 1518 //!!! Don't change this
--- /dev/null
+/**
+ * \file
+ * <!--
+ * This file is part of BeRTOS.
+ *
+ * Bertos is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * As a special exception, you may use this file as part of a free software
+ * library without restriction. Specifically, if other files instantiate
+ * templates or use macros or inline functions from this file, or you compile
+ * this file and link it with other files to produce an executable, this
+ * file does not by itself cause the resulting executable to be covered by
+ * the GNU General Public License. This exception does not however
+ * invalidate any other reasons why the executable file might be covered by
+ * the GNU General Public License.
+ *
+ * Copyright 2009 Develer S.r.l. (http://www.develer.com/)
+ * All Rights Reserved.
+ * -->
+ *
+ * \brief Definition for Davicom DM9161A ethernet phy.
+ *
+ * \author Francesco Sacchi <batt@develer.com>
+ */
+
+#ifndef DM9161A_H
+#define DM9161A_H
+
+#define NIC_PHY_ADDR 31
+#define NIC_PHY_ID 0x0181b8a0
+
+#define PHY_INIT() \
+ do { \
+ phy_pinGpio(); \
+ /* Disable RMII and TESTMODE */ \
+ phy_pinSet(PHY_MII_PINS & ~(PHY_COL_BIT | PHY_RXDV_BIT)); \
+ phy_resetPulse(); \
+ } while (0)
+#endif /* DM9161A_H */
--- /dev/null
+/**
+ * \file
+ * <!--
+ * This file is part of BeRTOS.
+ *
+ * Bertos is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * As a special exception, you may use this file as part of a free software
+ * library without restriction. Specifically, if other files instantiate
+ * templates or use macros or inline functions from this file, or you compile
+ * this file and link it with other files to produce an executable, this
+ * file does not by itself cause the resulting executable to be covered by
+ * the GNU General Public License. This exception does not however
+ * invalidate any other reasons why the executable file might be covered by
+ * the GNU General Public License.
+ *
+ * Copyright 2009 Develer S.r.l. (http://www.develer.com/)
+ * All Rights Reserved.
+ * -->
+ *
+ * \brief Definition for Natial DP83848I ethernet phy.
+ *
+ * \author Francesco Sacchi <batt@develer.com>
+ */
+
+#ifndef DP83848I_H
+#define DP83848I_H
+
+#define NIC_PHY_ADDR 1
+#define NIC_PHY_ID 0x20005C90
+
+#define PHY_INIT() \
+ do { \
+ /* Use defaults */ \
+ phy_pinThreeState(); \
+ phy_resetPulse(); \
+ } while (0)
+
+#endif /* DP83848I_H */
#define DRV_ETH_H
#include "hw/hw_eth.h"
+#include "cfg/cfg_eth.h"
+
+#include <drv/phy.h>
+
#include <cpu/types.h>
+
#define ETH_ADDR_LEN 6
#define ETH_HEAD_LEN 14
#define ETH_DATA_LEN 1500
#define ETH_FRAME_LEN (ETH_HEAD_LEN + ETH_DATA_LEN)
-
-#define ETH_TYPE_IP 0x0800
+#define ETH_TYPE_IP 0x0800
typedef union Ethernet
{
--- /dev/null
+/**
+ * \file
+ * <!--
+ * This file is part of BeRTOS.
+ *
+ * Bertos is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * As a special exception, you may use this file as part of a free software
+ * library without restriction. Specifically, if other files instantiate
+ * templates or use macros or inline functions from this file, or you compile
+ * this file and link it with other files to produce an executable, this
+ * file does not by itself cause the resulting executable to be covered by
+ * the GNU General Public License. This exception does not however
+ * invalidate any other reasons why the executable file might be covered by
+ * the GNU General Public License.
+ *
+ * Copyright 2011 Develer S.r.l. (http://www.develer.com/)
+ *
+ * -->
+ *
+ * \author Daniele Basile <asterix@develer.com>
+ *
+ * \brief PHY chip interface.
+ *
+ * $WIZ$
+ */
+
+#ifndef DRV_PHY_H
+#define DRV_PHY_H
+
+#include <cfg/cfg_eth.h>
+
+/**
+ * \name Supported PHY chip.
+ *
+ * List of supported PHY chip.
+ *
+ * $WIZ$ phy_chip_list = "DAVICOM_DM9161A", "NATIONAL_DP3848I"
+ * \{
+ */
+#define DAVICOM_DM9161A 0
+#define NATIONAL_DP3848I 1
+/** \} */
+
+#if CONFIG_PHY_CHIP == DAVICOM_DM9161A
+ #include <drv/dm9161a.h>
+#elif CONFIG_PHY_CHIP == NATIONAL_DP3848I
+ #include <drv/dp8348i.h>
+#else
+ #error No supported PHY chip was select.
+#endif
+
+#endif /* DRV_PHY_H */
extern uint8_t mac_addr[6];
-#endif // HW_ETH_H
+#define PHY_HW_INIT() do { /* Implement me! */ } while (0)
+
+#endif /* HW_ETH_H */
*/
#define ETH_LOG_FORMAT LOG_FMT_TERSE
+/**
+ * Select the supported phy chip.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "phy_chip_list"
+ */
+#define CONFIG_PHY_CHIP DAVICOM_DM9161A
+
+
#endif /* CFG_ETH_H */
*/
#define ETH_LOG_FORMAT LOG_FMT_TERSE
+/**
+ * Select the supported phy chip.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "phy_chip_list"
+ */
+#define CONFIG_PHY_CHIP DAVICOM_DM9161A
+
+
#endif /* CFG_ETH_H */
*/
#define ETH_LOG_FORMAT LOG_FMT_TERSE
+/**
+ * Select the supported phy chip.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "phy_chip_list"
+ */
+#define CONFIG_PHY_CHIP DAVICOM_DM9161A
+
+
#endif /* CFG_ETH_H */
*/
#define ETH_LOG_FORMAT LOG_FMT_TERSE
+/**
+ * Select the supported phy chip.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "phy_chip_list"
+ */
+#define CONFIG_PHY_CHIP DAVICOM_DM9161A
+
+
#endif /* CFG_ETH_H */
*/
#define ETH_LOG_FORMAT LOG_FMT_TERSE
+/**
+ * Select the supported phy chip.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "phy_chip_list"
+ */
+#define CONFIG_PHY_CHIP DAVICOM_DM9161A
+
+
#endif /* CFG_ETH_H */
*/
#define ETH_LOG_FORMAT LOG_FMT_TERSE
+/**
+ * Select the supported phy chip.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "phy_chip_list"
+ */
+#define CONFIG_PHY_CHIP DAVICOM_DM9161A
+
+
#endif /* CFG_ETH_H */
*/
#define ETH_LOG_FORMAT LOG_FMT_TERSE
+/**
+ * Select the supported phy chip.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "phy_chip_list"
+ */
+#define CONFIG_PHY_CHIP DAVICOM_DM9161A
+
+
#endif /* CFG_ETH_H */
*/
#define ETH_LOG_FORMAT LOG_FMT_TERSE
+/**
+ * Select the supported phy chip.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "phy_chip_list"
+ */
+#define CONFIG_PHY_CHIP DAVICOM_DM9161A
+
+
#endif /* CFG_ETH_H */
*/
#define ETH_LOG_FORMAT LOG_FMT_TERSE
+/**
+ * Select the supported phy chip.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "phy_chip_list"
+ */
+#define CONFIG_PHY_CHIP DAVICOM_DM9161A
+
+
#endif /* CFG_ETH_H */
*/
#define ETH_LOG_FORMAT LOG_FMT_TERSE
+/**
+ * Select the supported phy chip.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "phy_chip_list"
+ */
+#define CONFIG_PHY_CHIP DAVICOM_DM9161A
+
+
#endif /* CFG_ETH_H */
*/
#define ETH_LOG_FORMAT LOG_FMT_TERSE
+/**
+ * Select the supported phy chip.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "phy_chip_list"
+ */
+#define CONFIG_PHY_CHIP DAVICOM_DM9161A
+
+
#endif /* CFG_ETH_H */
*/
#define ETH_LOG_FORMAT LOG_FMT_TERSE
+/**
+ * Select the supported phy chip.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "phy_chip_list"
+ */
+#define CONFIG_PHY_CHIP DAVICOM_DM9161A
+
+
#endif /* CFG_ETH_H */
*/
#define ETH_LOG_FORMAT LOG_FMT_TERSE
+/**
+ * Select the supported phy chip.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "phy_chip_list"
+ */
+#define CONFIG_PHY_CHIP DAVICOM_DM9161A
+
+
#endif /* CFG_ETH_H */
*/
#define ETH_LOG_FORMAT LOG_FMT_TERSE
+/**
+ * Select the supported phy chip.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "phy_chip_list"
+ */
+#define CONFIG_PHY_CHIP DAVICOM_DM9161A
+
+
#endif /* CFG_ETH_H */
*/
#define ETH_LOG_FORMAT LOG_FMT_TERSE
+/**
+ * Select the supported phy chip.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "phy_chip_list"
+ */
+#define CONFIG_PHY_CHIP DAVICOM_DM9161A
+
+
#endif /* CFG_ETH_H */
*/
#define ETH_LOG_FORMAT LOG_FMT_TERSE
+/**
+ * Select the supported phy chip.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "phy_chip_list"
+ */
+#define CONFIG_PHY_CHIP DAVICOM_DM9161A
+
+
#endif /* CFG_ETH_H */
*/
#define ETH_LOG_FORMAT LOG_FMT_TERSE
+/**
+ * Select the supported phy chip.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "phy_chip_list"
+ */
+#define CONFIG_PHY_CHIP DAVICOM_DM9161A
+
+
#endif /* CFG_ETH_H */
*/
#define ETH_LOG_FORMAT LOG_FMT_TERSE
+/**
+ * Select the supported phy chip.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "phy_chip_list"
+ */
+#define CONFIG_PHY_CHIP DAVICOM_DM9161A
+
+
#endif /* CFG_ETH_H */
extern uint8_t mac_addr[6];
-#endif // HW_ETH_H
+#define PHY_HW_INIT() \
+ do { \
+ PIOB_OER = BV(18); \
+ PIOB_CODR = BV(18); \
+ PIOB_PER = BV(18); \
+ } while (0)
+
+#endif /* HW_ETH_H */
*/
#define ETH_LOG_FORMAT LOG_FMT_TERSE
+/**
+ * Select the supported phy chip.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "phy_chip_list"
+ */
+#define CONFIG_PHY_CHIP DAVICOM_DM9161A
+
+
#endif /* CFG_ETH_H */
*/
#define ETH_LOG_FORMAT LOG_FMT_TERSE
+/**
+ * Select the supported phy chip.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "phy_chip_list"
+ */
+#define CONFIG_PHY_CHIP DAVICOM_DM9161A
+
+
#endif /* CFG_ETH_H */
*/
#define ETH_LOG_FORMAT LOG_FMT_TERSE
+/**
+ * Select the supported phy chip.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "phy_chip_list"
+ */
+#define CONFIG_PHY_CHIP DAVICOM_DM9161A
+
+
#endif /* CFG_ETH_H */
*/
#define ETH_LOG_FORMAT LOG_FMT_TERSE
+/**
+ * Select the supported phy chip.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "phy_chip_list"
+ */
+#define CONFIG_PHY_CHIP DAVICOM_DM9161A
+
+
#endif /* CFG_ETH_H */
*/
#define ETH_LOG_FORMAT LOG_FMT_TERSE
+/**
+ * Select the supported phy chip.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "phy_chip_list"
+ */
+#define CONFIG_PHY_CHIP DAVICOM_DM9161A
+
+
#endif /* CFG_ETH_H */
*/
#define ETH_LOG_FORMAT LOG_FMT_TERSE
+/**
+ * Select the supported phy chip.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "phy_chip_list"
+ */
+#define CONFIG_PHY_CHIP DAVICOM_DM9161A
+
+
#endif /* CFG_ETH_H */
*/
#define ETH_LOG_FORMAT LOG_FMT_TERSE
+/**
+ * Select the supported phy chip.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "phy_chip_list"
+ */
+#define CONFIG_PHY_CHIP DAVICOM_DM9161A
+
+
#endif /* CFG_ETH_H */
*/
#define ETH_LOG_FORMAT LOG_FMT_TERSE
+/**
+ * Select the supported phy chip.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "phy_chip_list"
+ */
+#define CONFIG_PHY_CHIP DAVICOM_DM9161A
+
+
#endif /* CFG_ETH_H */
*/
#define ETH_LOG_FORMAT LOG_FMT_TERSE
+/**
+ * Select the supported phy chip.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "phy_chip_list"
+ */
+#define CONFIG_PHY_CHIP DAVICOM_DM9161A
+
+
#endif /* CFG_ETH_H */
*/
#define ETH_LOG_FORMAT LOG_FMT_TERSE
+/**
+ * Select the supported phy chip.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "phy_chip_list"
+ */
+#define CONFIG_PHY_CHIP DAVICOM_DM9161A
+
+
#endif /* CFG_ETH_H */
*/
#define ETH_LOG_FORMAT LOG_FMT_TERSE
+/**
+ * Select the supported phy chip.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "phy_chip_list"
+ */
+#define CONFIG_PHY_CHIP DAVICOM_DM9161A
+
+
#endif /* CFG_ETH_H */
*/
#define ETH_LOG_FORMAT LOG_FMT_TERSE
+/**
+ * Select the supported phy chip.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "phy_chip_list"
+ */
+#define CONFIG_PHY_CHIP DAVICOM_DM9161A
+
+
#endif /* CFG_ETH_H */
*/
#define ETH_LOG_FORMAT LOG_FMT_TERSE
+/**
+ * Select the supported phy chip.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "phy_chip_list"
+ */
+#define CONFIG_PHY_CHIP DAVICOM_DM9161A
+
+
#endif /* CFG_ETH_H */
*/
#define ETH_LOG_FORMAT LOG_FMT_TERSE
+/**
+ * Select the supported phy chip.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "phy_chip_list"
+ */
+#define CONFIG_PHY_CHIP DAVICOM_DM9161A
+
+
#endif /* CFG_ETH_H */
*/
#define ETH_LOG_FORMAT LOG_FMT_TERSE
+/**
+ * Select the supported phy chip.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "phy_chip_list"
+ */
+#define CONFIG_PHY_CHIP DAVICOM_DM9161A
+
+
#endif /* CFG_ETH_H */
*/
#define ETH_LOG_FORMAT LOG_FMT_TERSE
+/**
+ * Select the supported phy chip.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "phy_chip_list"
+ */
+#define CONFIG_PHY_CHIP DAVICOM_DM9161A
+
+
#endif /* CFG_ETH_H */
*/
#define ETH_LOG_FORMAT LOG_FMT_TERSE
+/**
+ * Select the supported phy chip.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "phy_chip_list"
+ */
+#define CONFIG_PHY_CHIP DAVICOM_DM9161A
+
+
#endif /* CFG_ETH_H */
*/
#define ETH_LOG_FORMAT LOG_FMT_TERSE
+/**
+ * Select the supported phy chip.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "phy_chip_list"
+ */
+#define CONFIG_PHY_CHIP DAVICOM_DM9161A
+
+
#endif /* CFG_ETH_H */
*/
#define ETH_LOG_FORMAT LOG_FMT_TERSE
+/**
+ * Select the supported phy chip.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "phy_chip_list"
+ */
+#define CONFIG_PHY_CHIP DAVICOM_DM9161A
+
+
#endif /* CFG_ETH_H */
*/
#define ETH_LOG_FORMAT LOG_FMT_TERSE
+/**
+ * Select the supported phy chip.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "phy_chip_list"
+ */
+#define CONFIG_PHY_CHIP DAVICOM_DM9161A
+
+
#endif /* CFG_ETH_H */
*/
#define ETH_LOG_FORMAT LOG_FMT_TERSE
+/**
+ * Select the supported phy chip.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "phy_chip_list"
+ */
+#define CONFIG_PHY_CHIP DAVICOM_DM9161A
+
+
#endif /* CFG_ETH_H */
*/
#define ETH_LOG_FORMAT LOG_FMT_TERSE
+/**
+ * Select the supported phy chip.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "phy_chip_list"
+ */
+#define CONFIG_PHY_CHIP DAVICOM_DM9161A
+
+
#endif /* CFG_ETH_H */
projects / bertos.git / commitdiff