lm3s1968-gpio: coding style fixes.

git-svn-id: https://src.develer.com/svnoss/bertos/trunk@3416 38d2e660-2303-0410-9eaa-f027e97ec537

diff --git a/bertos/cpu/cortex-m3/drv/gpio_lm3s.c b/bertos/cpu/cortex-m3/drv/gpio_lm3s.c
index 2f887b59243f16f9b8a21bc8a81f065677085cb9..653fd1e99e18676d9198507ffbf7fcd0630607bc 100644 (file)
--- a/bertos/cpu/cortex-m3/drv/gpio_lm3s.c
+++ b/bertos/cpu/cortex-m3/drv/gpio_lm3s.c
@@ -40,21 +40,9 @@
 #include <io/lm3s.h>
 #include "gpio_lm3s.h"
 
-/**
- * Configure a GPIO pin
- *
- * \param port Base address of the GPIO port
- * \param pins Bit-packed representation of the pin(s)
- * \param mode Pin(s) configuration mode
- * \param strength Output drive strength
- * \param type Pin(s) type
- *
- * Return 0 on success, otherwise a negative value.
- */
-int lm3s_gpio_pin_config(uint32_t port, uint8_t pins,
-               uint32_t mode, uint32_t strength, uint32_t type)
+/* Set the pin(s) direction and mode */
+INLINE int lm3s_gpioPinConfigMode(uint32_t port, uint8_t pins, uint32_t mode)
 {
-       /* Set the pin direction and mode */
        switch (mode)
        {
        case GPIO_DIR_MODE_IN:
@@ -73,7 +61,13 @@ int lm3s_gpio_pin_config(uint32_t port, uint8_t pins,
                ASSERT(0);
                return -1;
        }
-       /* Set the output strength */
+       return 0;
+}
+
+/* Set the pin(s) output strength */
+INLINE int
+lm3s_gpioPinConfigStrength(uint32_t port, uint8_t pins, uint32_t strength)
+{
        switch (strength)
        {
        case GPIO_STRENGTH_2MA:
@@ -104,9 +98,21 @@ int lm3s_gpio_pin_config(uint32_t port, uint8_t pins,
                ASSERT(0);
                return -1;
        }
-       /* Set the pin type */
+       return 0;
+}
+
+/* Set the pin(s) type */
+INLINE int lm3s_gpioPinConfigType(uint32_t port, uint8_t pins, uint32_t type)
+{
        switch (type)
        {
+       case GPIO_PIN_TYPE_ANALOG:
+               HWREG(port + GPIO_O_ODR)   &= ~pins;
+               HWREG(port + GPIO_O_PUR)   &= ~pins;
+               HWREG(port + GPIO_O_PDR)   &= ~pins;
+               HWREG(port + GPIO_O_DEN)   &= ~pins;
+               HWREG(port + GPIO_O_AMSEL) |= pins;
+               break;
        case GPIO_PIN_TYPE_STD:
                HWREG(port + GPIO_O_ODR)   &= ~pins;
                HWREG(port + GPIO_O_PUR)   &= ~pins;
@@ -149,15 +155,37 @@ int lm3s_gpio_pin_config(uint32_t port, uint8_t pins,
                HWREG(port + GPIO_O_DEN)   |= pins;
                HWREG(port + GPIO_O_AMSEL) &= ~pins;
                break;
-       case GPIO_PIN_TYPE_ANALOG:
-               HWREG(port + GPIO_O_ODR)   &= ~pins;
-               HWREG(port + GPIO_O_PUR)   &= ~pins;
-               HWREG(port + GPIO_O_PDR)   &= ~pins;
-               HWREG(port + GPIO_O_DEN)   &= ~pins;
-               HWREG(port + GPIO_O_AMSEL) |= pins;
        default:
                ASSERT(0);
                return -1;
        }
        return 0;
 }
+
+/**
+ * Configure a GPIO pin
+ *
+ * \param port Base address of the GPIO port
+ * \param pins Bit-packed representation of the pin(s)
+ * \param mode Pin(s) configuration mode
+ * \param strength Output drive strength
+ * \param type Pin(s) type
+ *
+ * Return 0 on success, otherwise a negative value.
+ */
+int lm3s_gpioPinConfig(uint32_t port, uint8_t pins,
+               uint32_t mode, uint32_t strength, uint32_t type)
+{
+       int ret;
+
+       ret = lm3s_gpioPinConfigMode(port, pins, mode);
+       if (UNLIKELY(ret < 0))
+               return ret;
+       ret = lm3s_gpioPinConfigStrength(port, pins, strength);
+       if (UNLIKELY(ret < 0))
+               return ret;
+       ret = lm3s_gpioPinConfigType(port, pins, type);
+       if (UNLIKELY(ret < 0))
+               return ret;
+       return 0;
+}

diff --git a/bertos/cpu/cortex-m3/drv/gpio_lm3s.h b/bertos/cpu/cortex-m3/drv/gpio_lm3s.h
index de1f397eb5d51033f6a036d8d984a6a2aaeaa71f..9ff6b56b8bfd36e92c2da5d57314b4598b86a45d 100644 (file)
--- a/bertos/cpu/cortex-m3/drv/gpio_lm3s.h
+++ b/bertos/cpu/cortex-m3/drv/gpio_lm3s.h
@@ -42,42 +42,50 @@
  * GPIO mode
  */
 /*\{*/
-#define GPIO_DIR_MODE_IN        0x00000000  //< Pin is a GPIO input
-#define GPIO_DIR_MODE_OUT       0x00000001  //< Pin is a GPIO output
-#define GPIO_DIR_MODE_HW        0x00000002  //< Pin is a peripheral function
+enum
+{
+       GPIO_DIR_MODE_IN = 0, //< Pin is a GPIO input
+       GPIO_DIR_MODE_OUT,    //< Pin is a GPIO output
+       GPIO_DIR_MODE_HW,     //< Pin is a peripheral function
+};
 /*\}*/
 
 /**
  * GPIO strenght
  */
 /*\{*/
-#define GPIO_STRENGTH_2MA       0x00000001  //< 2mA drive strength
-#define GPIO_STRENGTH_4MA       0x00000002  //< 4mA drive strength
-#define GPIO_STRENGTH_8MA       0x00000004  //< 8mA drive strength
-#define GPIO_STRENGTH_8MA_SC    0x0000000C  //< 8mA drive with slew rate control
+enum
+{
+       GPIO_STRENGTH_2MA = 0, //< 2mA drive strength
+       GPIO_STRENGTH_4MA,     //< 4mA drive strength
+       GPIO_STRENGTH_8MA,     //< 8mA drive strength
+       GPIO_STRENGTH_8MA_SC,  //< 8mA drive with slew rate control
+};
 /*\}*/
 
 /**
  * GPIO type
  */
 /*\{*/
-#define GPIO_PIN_TYPE_STD       0x00000008  //< Push-pull
-#define GPIO_PIN_TYPE_STD_WPU   0x0000000A  //< Push-pull with weak pull-up
-#define GPIO_PIN_TYPE_STD_WPD   0x0000000C  //< Push-pull with weak pull-down
-#define GPIO_PIN_TYPE_OD        0x00000009  //< Open-drain
-#define GPIO_PIN_TYPE_OD_WPU    0x0000000B  //< Open-drain with weak pull-up
-#define GPIO_PIN_TYPE_OD_WPD    0x0000000D  //< Open-drain with weak pull-down
-#define GPIO_PIN_TYPE_ANALOG    0x00000000  //< Analog comparator
+enum
+{
+       GPIO_PIN_TYPE_ANALOG = 0, //< Analog comparator
+       GPIO_PIN_TYPE_STD,        //< Push-pull
+       GPIO_PIN_TYPE_STD_WPU,    //< Push-pull with weak pull-up
+       GPIO_PIN_TYPE_STD_WPD,    //< Push-pull with weak pull-down
+       GPIO_PIN_TYPE_OD,         //< Open-drain
+       GPIO_PIN_TYPE_OD_WPU,     //< Open-drain with weak pull-up
+       GPIO_PIN_TYPE_OD_WPD,     //< Open-drain with weak pull-down
+};
 /*\}*/
 
 /* Write a value to the specified pin(s) */
-INLINE void lm3s_gpio_pin_write(uint32_t port, uint8_t pins, uint8_t val)
+INLINE void lm3s_gpioPinWrite(uint32_t port, uint8_t pins, uint8_t val)
 {
        HWREG(port + (GPIO_O_DATA + (pins << 2))) = val;
 }
 
-int lm3s_gpio_pin_config(uint32_t port, uint8_t pins,
+int lm3s_gpioPinConfig(uint32_t port, uint8_t pins,
                uint32_t mode, uint32_t strength, uint32_t type);
-void lm3s_gpio_pin_write(uint32_t port, uint8_t pins, uint8_t val);
 
 #endif /* GPIO_LM3S_H */

diff --git a/bertos/cpu/cortex-m3/drv/kdebug_lm3s.c b/bertos/cpu/cortex-m3/drv/kdebug_lm3s.c
index d7be790a0a59090dcb2205b82774ab5b92e767e2..65c1dccb46512e36ccc917ee349840dccf6355a7 100644 (file)
--- a/bertos/cpu/cortex-m3/drv/kdebug_lm3s.c
+++ b/bertos/cpu/cortex-m3/drv/kdebug_lm3s.c
@@ -128,7 +128,7 @@ INLINE void kdbg_hw_init(void)
        lm3s_busyWait(512);
 
        /* Set GPIO A0 and A1 as UART pins */
-       lm3s_gpio_pin_config(GPIO_PORTA_BASE, BV(0) | BV(1),
+       lm3s_gpioPinConfig(GPIO_PORTA_BASE, BV(0) | BV(1),
                        GPIO_DIR_MODE_HW, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
        /* 115.200, 8-bit word, no parity, one stop bit */
        uart_config(UART0_BASE, CONFIG_KDEBUG_BAUDRATE, UART_LCRH_WLEN_8);

diff --git a/examples/lm3s1968/hw/hw_lcd.h b/examples/lm3s1968/hw/hw_lcd.h
index 4a6ceb9d163f48a63006c9162b1032c5a6d29494..ed2ede9e251cdc4b3e04d79059c043221fd10b48 100644 (file)
--- a/examples/lm3s1968/hw/hw_lcd.h
+++ b/examples/lm3s1968/hw/hw_lcd.h
@@ -69,11 +69,11 @@
  */
 /* Enter command mode */
 #define LCD_SET_COMMAND() \
-       lm3s_gpio_pin_write(GPIO_PORTH_BASE, GPIO_OLEDDC_PIN, 0)
+       lm3s_gpioPinWrite(GPIO_PORTH_BASE, GPIO_OLEDDC_PIN, 0)
 
 /* Enter data mode */
 #define LCD_SET_DATA() \
-       lm3s_gpio_pin_write(GPIO_PORTH_BASE, GPIO_OLEDDC_PIN, GPIO_OLEDDC_PIN)
+       lm3s_gpioPinWrite(GPIO_PORTH_BASE, GPIO_OLEDDC_PIN, GPIO_OLEDDC_PIN)
 
 /* Send data to the display */
 #define LCD_WRITE(x)   lm3s_ssiWriteFrame(SSI0_BASE, x)
@@ -101,16 +101,16 @@ INLINE void lcd_bus_init(void)
        lm3s_busyWait(512);
 
        /* Configure the SSI0CLK and SSIOTX pins for SSI operation. */
-       lm3s_gpio_pin_config(GPIO_PORTA_BASE, BV(2) | BV(3) | BV(5),
+       lm3s_gpioPinConfig(GPIO_PORTA_BASE, BV(2) | BV(3) | BV(5),
                GPIO_DIR_MODE_HW, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD_WPU);
        /*
         * Configure the GPIO port pin used as a D/C# signal (data/command
         * control) for OLED device, and the port pin used to enable power to
         * the OLED panel.
         */
-       lm3s_gpio_pin_config(GPIO_PORTH_BASE, GPIO_OLEDDC_PIN | GPIO_OLEDEN_PIN,
+       lm3s_gpioPinConfig(GPIO_PORTH_BASE, GPIO_OLEDDC_PIN | GPIO_OLEDEN_PIN,
                GPIO_DIR_MODE_OUT, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD);
-       lm3s_gpio_pin_write(GPIO_PORTH_BASE, GPIO_OLEDDC_PIN | GPIO_OLEDEN_PIN,
+       lm3s_gpioPinWrite(GPIO_PORTH_BASE, GPIO_OLEDDC_PIN | GPIO_OLEDEN_PIN,
                        GPIO_OLEDDC_PIN | GPIO_OLEDEN_PIN);
 
        /* Configure the SSI0 port for master mode */
@@ -120,7 +120,7 @@ INLINE void lcd_bus_init(void)
         * Configure the GPIO port pin used as a D/Cn signal for OLED device,
         * and the port pin used to enable power to the OLED panel.
         */
-       lm3s_gpio_pin_config(GPIO_PORTA_BASE, GPIO_OLEDEN_PIN,
+       lm3s_gpioPinConfig(GPIO_PORTA_BASE, GPIO_OLEDEN_PIN,
                GPIO_DIR_MODE_HW, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD_WPU);
 
        /* Drain the SSI RX FIFO */