Add mask for i2c events. Reformat.

git-svn-id: https://src.develer.com/svnoss/bertos/branches/i2c@4022 38d2e660-2303-0410-9eaa-f027e97ec537

diff --git a/bertos/cpu/cortex-m3/io/lm3s_i2c.h b/bertos/cpu/cortex-m3/io/lm3s_i2c.h
index 5ada60bdf29309a8fa55452dabaa3289df7587c0..6e4eb03a0e7c60c5b35f5dcb306e49f84ccdb5a4 100644 (file)
--- a/bertos/cpu/cortex-m3/io/lm3s_i2c.h
+++ b/bertos/cpu/cortex-m3/io/lm3s_i2c.h
@@ -62,6 +62,8 @@
 #define I2C_MSA_SA_M            0x000000FE  ///< I2C Slave Address
 #define I2C_MSA_RS              0x00000001  ///< Receive not send
 #define I2C_MSA_SA_S            1
+#define I2C_MSA_ADDS            0           ///< Set address write bit
+#define I2C_MSA_ADDR            1           ///< Set address read bit
 
 
 /* The following are defines for the bit fields in the I2C_O_SOAR register. */
@@ -150,88 +152,111 @@
 #define I2C_MCR_LPBK            0x00000001  ///< I2C Loopback
 
 
+
+#define I2C_MASTER_CMD_SINGLE_SEND                                            \\r
+                                0x00000007\r
+#define I2C_MASTER_CMD_SINGLE_RECEIVE                                         \\r
+                                0x00000007\r
+#define I2C_MASTER_CMD_BURST_SEND_START                                       \\r
+                                0x00000003\r
+#define I2C_MASTER_CMD_BURST_SEND_CONT                                        \\r
+                                0x00000001\r
+#define I2C_MASTER_CMD_BURST_SEND_FINISH                                      \\r
+                                0x00000005\r
+#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP                                  \\r
+                                0x00000004\r
+#define I2C_MASTER_CMD_BURST_RECEIVE_START                                    \\r
+                                0x0000000b\r
+#define I2C_MASTER_CMD_BURST_RECEIVE_CONT                                     \\r
+                                0x00000009\r
+#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH                                   \\r
+                                0x00000005\r
+#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP                               \\r
+                                0x00000004
+
+
 /* The following definitions are deprecated. */
 
 #ifndef DEPRECATED
 
-#define I2C_O_SLAVE             0x00000800  ///< Offset from master to slave
+       #define I2C_O_SLAVE             0x00000800  ///< Offset from master to slave
 
-#define I2C_SIMR_IM             0x00000001  ///< Interrupt Mask
+       #define I2C_SIMR_IM             0x00000001  ///< Interrupt Mask
 
-#define I2C_SRIS_RIS            0x00000001  ///< Raw Interrupt Status
+       #define I2C_SRIS_RIS            0x00000001  ///< Raw Interrupt Status
 
-#define I2C_SMIS_MIS            0x00000001  ///< Masked Interrupt Status
+       #define I2C_SMIS_MIS            0x00000001  ///< Masked Interrupt Status
 
-#define I2C_SICR_IC             0x00000001  ///< Clear Interrupt
+       #define I2C_SICR_IC             0x00000001  ///< Clear Interrupt
 
-#define I2C_MASTER_O_SA         0x00000000  ///< Slave address register
-#define I2C_MASTER_O_CS         0x00000004  ///< Control and Status register
-#define I2C_MASTER_O_DR         0x00000008  ///< Data register
-#define I2C_MASTER_O_TPR        0x0000000C  ///< Timer period register
-#define I2C_MASTER_O_IMR        0x00000010  ///< Interrupt mask register
-#define I2C_MASTER_O_RIS        0x00000014  ///< Raw interrupt status register
-#define I2C_MASTER_O_MIS        0x00000018  ///< Masked interrupt status reg
-#define I2C_MASTER_O_MICR       0x0000001C  ///< Interrupt clear register
-#define I2C_MASTER_O_CR         0x00000020  ///< Configuration register
+       #define I2C_MASTER_O_SA         0x00000000  ///< Slave address register
+       #define I2C_MASTER_O_CS         0x00000004  ///< Control and Status register
+       #define I2C_MASTER_O_DR         0x00000008  ///< Data register
+       #define I2C_MASTER_O_TPR        0x0000000C  ///< Timer period register
+       #define I2C_MASTER_O_IMR        0x00000010  ///< Interrupt mask register
+       #define I2C_MASTER_O_RIS        0x00000014  ///< Raw interrupt status register
+       #define I2C_MASTER_O_MIS        0x00000018  ///< Masked interrupt status reg
+       #define I2C_MASTER_O_MICR       0x0000001C  ///< Interrupt clear register
+       #define I2C_MASTER_O_CR         0x00000020  ///< Configuration register
 
-#define I2C_SLAVE_O_SICR        0x00000018  ///< Interrupt clear register
-#define I2C_SLAVE_O_MIS         0x00000014  ///< Masked interrupt status reg
-#define I2C_SLAVE_O_RIS         0x00000010  ///< Raw interrupt status register
-#define I2C_SLAVE_O_IM          0x0000000C  ///< Interrupt mask register
-#define I2C_SLAVE_O_DR          0x00000008  ///< Data register
-#define I2C_SLAVE_O_CSR         0x00000004  ///< Control/Status register
-#define I2C_SLAVE_O_OAR         0x00000000  ///< Own address register
+       #define I2C_SLAVE_O_SICR        0x00000018  ///< Interrupt clear register
+       #define I2C_SLAVE_O_MIS         0x00000014  ///< Masked interrupt status reg
+       #define I2C_SLAVE_O_RIS         0x00000010  ///< Raw interrupt status register
+       #define I2C_SLAVE_O_IM          0x0000000C  ///< Interrupt mask register
+       #define I2C_SLAVE_O_DR          0x00000008  ///< Data register
+       #define I2C_SLAVE_O_CSR         0x00000004  ///< Control/Status register
+       #define I2C_SLAVE_O_OAR         0x00000000  ///< Own address register
 
-#define I2C_MASTER_SA_SA_MASK   0x000000FE  ///< Slave address
-#define I2C_MASTER_SA_RS        0x00000001  ///< Receive/send
-#define I2C_MASTER_SA_SA_SHIFT  1
+       #define I2C_MASTER_SA_SA_MASK   0x000000FE  ///< Slave address
+       #define I2C_MASTER_SA_RS        0x00000001  ///< Receive/send
+       #define I2C_MASTER_SA_SA_SHIFT  1
 
-#define I2C_MASTER_CS_BUS_BUSY  0x00000040  ///< Bus busy
-#define I2C_MASTER_CS_IDLE      0x00000020  ///< Idle
-#define I2C_MASTER_CS_ERR_MASK  0x0000001C
-#define I2C_MASTER_CS_BUSY      0x00000001  ///< Controller is TX/RX data
-#define I2C_MASTER_CS_ERROR     0x00000002  ///< Error occurred
-#define I2C_MASTER_CS_ADDR_ACK  0x00000004  ///< Address byte not acknowledged
-#define I2C_MASTER_CS_DATA_ACK  0x00000008  ///< Data byte not acknowledged
-#define I2C_MASTER_CS_ARB_LOST  0x00000010  ///< Lost arbitration
-#define I2C_MASTER_CS_ACK       0x00000008  ///< Acknowlegde
-#define I2C_MASTER_CS_STOP      0x00000004  ///< Stop
-#define I2C_MASTER_CS_START     0x00000002  ///< Start
-#define I2C_MASTER_CS_RUN       0x00000001  ///< Run
+       #define I2C_MASTER_CS_BUS_BUSY  0x00000040  ///< Bus busy
+       #define I2C_MASTER_CS_IDLE      0x00000020  ///< Idle
+       #define I2C_MASTER_CS_ERR_MASK  0x0000001C
+       #define I2C_MASTER_CS_BUSY      0x00000001  ///< Controller is TX/RX data
+       #define I2C_MASTER_CS_ERROR     0x00000002  ///< Error occurred
+       #define I2C_MASTER_CS_ADDR_ACK  0x00000004  ///< Address byte not acknowledged
+       #define I2C_MASTER_CS_DATA_ACK  0x00000008  ///< Data byte not acknowledged
+       #define I2C_MASTER_CS_ARB_LOST  0x00000010  ///< Lost arbitration
+       #define I2C_MASTER_CS_ACK       0x00000008  ///< Acknowlegde
+       #define I2C_MASTER_CS_STOP      0x00000004  ///< Stop
+       #define I2C_MASTER_CS_START     0x00000002  ///< Start
+       #define I2C_MASTER_CS_RUN       0x00000001  ///< Run
 
 
-#define I2C_SCL_FAST            400000      ///< SCL fast frequency
-#define I2C_SCL_STANDARD        100000      ///< SCL standard frequency
-#define I2C_MASTER_TPR_SCL_LP   0x00000006  ///< SCL low period
-#define I2C_MASTER_TPR_SCL_HP   0x00000004  ///< SCL high period
-#define I2C_MASTER_TPR_SCL      (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP)
+       #define I2C_SCL_FAST            400000      ///< SCL fast frequency
+       #define I2C_SCL_STANDARD        100000      ///< SCL standard frequency
+       #define I2C_MASTER_TPR_SCL_LP   0x00000006  ///< SCL low period
+       #define I2C_MASTER_TPR_SCL_HP   0x00000004  ///< SCL high period
+       #define I2C_MASTER_TPR_SCL      (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP)
 
-#define I2C_MASTER_IMR_IM       0x00000001  ///< Master interrupt mask
+       #define I2C_MASTER_IMR_IM       0x00000001  ///< Master interrupt mask
 
-#define I2C_MASTER_RIS_RIS      0x00000001  ///< Master raw interrupt status
+       #define I2C_MASTER_RIS_RIS      0x00000001  ///< Master raw interrupt status
 
-#define I2C_MASTER_MIS_MIS      0x00000001  ///< Master masked interrupt status
+       #define I2C_MASTER_MIS_MIS      0x00000001  ///< Master masked interrupt status
 
-#define I2C_MASTER_MICR_IC      0x00000001  ///< Master interrupt clear
+       #define I2C_MASTER_MICR_IC      0x00000001  ///< Master interrupt clear
 
-#define I2C_MASTER_CR_SFE       0x00000020  ///< Slave function enable
-#define I2C_MASTER_CR_MFE       0x00000010  ///< Master function enable
-#define I2C_MASTER_CR_LPBK      0x00000001  ///< Loopback enable
+       #define I2C_MASTER_CR_SFE       0x00000020  ///< Slave function enable
+       #define I2C_MASTER_CR_MFE       0x00000010  ///< Master function enable
+       #define I2C_MASTER_CR_LPBK      0x00000001  ///< Loopback enable
 
-#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F  ///< Slave address
+       #define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F  ///< Slave address
 
-#define I2C_SLAVE_CSR_FBR       0x00000004  ///< First byte received from master
-#define I2C_SLAVE_CSR_TREQ      0x00000002  ///< Transmit request received
-#define I2C_SLAVE_CSR_DA        0x00000001  ///< Enable the device
-#define I2C_SLAVE_CSR_RREQ      0x00000001  ///< Receive data from I2C master
+       #define I2C_SLAVE_CSR_FBR       0x00000004  ///< First byte received from master
+       #define I2C_SLAVE_CSR_TREQ      0x00000002  ///< Transmit request received
+       #define I2C_SLAVE_CSR_DA        0x00000001  ///< Enable the device
+       #define I2C_SLAVE_CSR_RREQ      0x00000001  ///< Receive data from I2C master
 
-#define I2C_SLAVE_IMR_IM        0x00000001  ///< Slave interrupt mask
+       #define I2C_SLAVE_IMR_IM        0x00000001  ///< Slave interrupt mask
 
-#define I2C_SLAVE_RIS_RIS       0x00000001  ///< Slave raw interrupt status
+       #define I2C_SLAVE_RIS_RIS       0x00000001  ///< Slave raw interrupt status
 
-#define I2C_SLAVE_MIS_MIS       0x00000001  ///< Slave masked interrupt status
+       #define I2C_SLAVE_MIS_MIS       0x00000001  ///< Slave masked interrupt status
 
-#define I2C_SLAVE_SICR_IC       0x00000001  ///< Slave interrupt clear
+       #define I2C_SLAVE_SICR_IC       0x00000001  ///< Slave interrupt clear
 
 #endif