Updated default crystal and CPU frequency.

The previous crystal value didn't exist. Fixed default CPU frequency
and crystal value.

git-svn-id: https://src.develer.com/svnoss/bertos/trunk@4696 38d2e660-2303-0410-9eaa-f027e97ec537

diff --git a/bertos/cpu/arm/hw/crtat91sam7_rom.S b/bertos/cpu/arm/hw/crtat91sam7_rom.S
index 0282785dd8a94c800c6239b7575dc346543a2790..51635fde4cb36b16a6ff32297bfea069d8989182 100644 (file)
--- a/bertos/cpu/arm/hw/crtat91sam7_rom.S
+++ b/bertos/cpu/arm/hw/crtat91sam7_rom.S
@@ -73,18 +73,18 @@
 #include "cfg/cfg_arch.h"
 
 
-#if CPU_FREQ != 48023000L
+#if CPU_FREQ != 48054857L
        /* Avoid errors on nightly test */
        #if !defined(ARCH_NIGHTTEST) || !(ARCH & ARCH_NIGHTTEST)
-               #warning Clock registers set for 48.023MHz operation, revise following code if you want a different clock.
+               #warning Clock registers set for 48.055MHz operation, revise following code if you want a different clock.
        #endif
 #endif
 
 
 #if CPU_ARM_SAM7S_LARGE || CPU_ARM_SAM7X
        /*
-        * With a 18.420MHz cristal, master clock is:
-        * (((18.420 * PLL_MUL_VAL + 1) / PLL_DIV_VAL) / AT91MCK_PRES) = 48.023MHz
+        * With a 18.432MHz cristal, master clock is:
+        * (((18.432 * (PLL_MUL_VAL + 1)) / PLL_DIV_VAL) / AT91MCK_PRES) = 48.055MHz
         */
        #define PLL_MUL_VAL  72  /**< Real multiplier value is PLL_MUL_VAL + 1! */
        #define PLL_DIV_VAL  14

diff --git a/bertos/cpu/arm/hw/init_at91.c b/bertos/cpu/arm/hw/init_at91.c
index 1bba1c223e044aaceecb5ebe4570b7ecef5cc186..fc7ffaf47ed265935de926ce8ec61d98e89ccf3a 100644 (file)
--- a/bertos/cpu/arm/hw/init_at91.c
+++ b/bertos/cpu/arm/hw/init_at91.c
@@ -41,19 +41,19 @@
 
 #define USE_FIXED_PLL 1
 
-#define XTAL_FREQ 18420000UL
+#define XTAL_FREQ 18432000UL
 
 #if USE_FIXED_PLL
-       #if CPU_FREQ != 48023000L
+       #if CPU_FREQ != 48054857L
                /* Avoid errors on nightly test */
                #if !defined(ARCH_NIGHTTEST) || !(ARCH & ARCH_NIGHTTEST)
-                       #warning Clock registers set for 48.023MHz operation, revise following code if you want a different clock.
+                       #warning Clock registers set for 48.055MHz operation, revise following code if you want a different clock.
                #endif
        #endif
 
        /*
-        * With a 18.420MHz cristal, master clock is:
-        * (((18.420 * PLL_MUL_VAL + 1) / PLL_DIV_VAL) / AT91MCK_PRES) = 48.023MHz
+        * With a 18.432MHz cristal, master clock is:
+        * (((18.432 * (PLL_MUL_VAL + 1)) / PLL_DIV_VAL) / AT91MCK_PRES) = 48.055MHz
         */
        #define PLL_MUL_VAL  72  /**< Real multiplier value is PLL_MUL_VAL + 1! */
        #define PLL_DIV_VAL  14

diff --git a/bertos/cpu/arm/hw/pll_at91.h b/bertos/cpu/arm/hw/pll_at91.h
index 50f4a0c435f425bc513a4833619025f7dd7eb8d3..9bf05f824cdd859a51b67e4f4c3c7049e120ad5d 100644 (file)
--- a/bertos/cpu/arm/hw/pll_at91.h
+++ b/bertos/cpu/arm/hw/pll_at91.h
@@ -141,7 +141,7 @@
 int main(int argc, char *argv[])
 {
     int32_t m, d, k;
-    PLL_CALC(18420000, 48023000, &m, &d, &k);
+    PLL_CALC(18432000, 48054857, &m, &d, &k);
 
     if (__builtin_constant_p(m) && __builtin_constant_p(k) && __builtin_constant_p(d))
         printf("SUCCESS -- compile time evaluation\n");

diff --git a/bertos/cpu/arm/info/at91sam7.common b/bertos/cpu/arm/info/at91sam7.common
index 0026de91a2da703da54cc6005b90721de792d9fc..beefc0e614b551542d56755329c2bd0d87a494a0 100644 (file)
--- a/bertos/cpu/arm/info/at91sam7.common
+++ b/bertos/cpu/arm/info/at91sam7.common
@@ -61,7 +61,7 @@ MK_PROGRAMMER_CPU = "at91sam7"
 MK_CPU = CORE_CPU
 
 # CPU default clock frequency
-CPU_DEFAULT_FREQ = "48023000UL"
+CPU_DEFAULT_FREQ = "48054857UL"
 
 # Special CPU related tags.
 CPU_TAGS = ["at91", CORE_CPU, TOOLCHAIN]