Implement i2c init.

git-svn-id: https://src.develer.com/svnoss/bertos/trunk@3970 38d2e660-2303-0410-9eaa-f027e97ec537

diff --git a/bertos/cpu/cortex-m3/drv/i2c_stm32.c b/bertos/cpu/cortex-m3/drv/i2c_stm32.c
index ee3a60e0843a36d93240af0afe60c3c055b619b0..4c519a59863b04f7f686d69a82ca36c0b24a5bf9 100644 (file)
--- a/bertos/cpu/cortex-m3/drv/i2c_stm32.c
+++ b/bertos/cpu/cortex-m3/drv/i2c_stm32.c
@@ -26,7 +26,7 @@
  * invalidate any other reasons why the executable file might be covered by
  * the GNU General Public License.
  *
- * Copyright 2003, 2004, 2005 Develer S.r.l. (http://www.develer.com/)
+ * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
  *
  * -->
  *
@@ -45,8 +45,15 @@
 #include <cfg/macros.h> // BV()
 #include <cfg/module.h>
 
+#include <drv/gpio_stm32.h>
+#include <drv/irq_cm3.h>
+#include <drv/clock_stm32.h>
 #include <drv/i2c.h>
 
+#include <io/stm32.h>
+
+struct stm32_i2c *i2c = (struct stm32_i2c *)I2C1_BASE;
+
 /**
  * Send START condition on the bus.
  *
@@ -54,8 +61,10 @@
  */
 static bool i2c_builtin_start(void)
 {
+       i2c->CR1 |= CR1_START_SET;
 
-       return false;
+       return ((i2c->SR1 & (BV(SR1_BUSY) | BV(SR1_MSL))) &
+                               (i2c->SR2 & BV(SR2_SB)));
 }
 
 
@@ -68,6 +77,10 @@ static bool i2c_builtin_start(void)
  */
 bool i2c_builtin_start_w(uint8_t id)
 {
+       id &=  OAR1_ADD0_RESET;
+       while (i2c_builtin_start())
+       {
+       }
        return false;
 }
 
@@ -82,6 +95,7 @@ bool i2c_builtin_start_w(uint8_t id)
 bool i2c_builtin_start_r(uint8_t id)
 {
 
+       id |=  OAR1_ADD0_SET;
        return false;
 }
 
@@ -91,7 +105,7 @@ bool i2c_builtin_start_r(uint8_t id)
  */
 void i2c_builtin_stop(void)
 {
-
+       i2c->CR1 |= CR1_STOP_SET;
 }
 
 
@@ -124,9 +138,37 @@ int i2c_builtin_get(bool ack)
 MOD_DEFINE(i2c);
 
 /**
- * Initialize TWI module.
+ * Initialize I2C module.
  */
 void i2c_builtin_init(void)
 {
        MOD_INIT(i2c);
+
+       RCC->APB2ENR |= RCC_APB2_GPIOB;
+       RCC->APB1ENR |= RCC_APB1_I2C1;
+
+       stm32_gpioPinConfig((struct stm32_gpio *)GPIOB_BASE, GPIO_I2C1_SCL_PIN,
+                               GPIO_MODE_AF_OD, GPIO_SPEED_50MHZ);
+
+       stm32_gpioPinConfig((struct stm32_gpio *)GPIOB_BASE, GPIO_I2C1_SDA_PIN,
+                               GPIO_MODE_AF_OD, GPIO_SPEED_50MHZ);
+
+       i2c->CR1 = 0;
+       i2c->CR2 = 0;
+       i2c->CCR = 0;
+       i2c->TRISE = 0;
+       i2c->OAR1 = 0;
+
+       i2c->CR2 |= CR2_FREQ_36MHZ;
+
+       /* Configure spi in standard mode */
+       #if CONFIG_I2C_FREQ <= 100000
+               i2c->TRISE |= (CR2_FREQ_36MHZ + 1);
+               i2c->CCR |= 4;
+       #else
+               #error fast mode not supported
+       #endif
+
+       i2c->CR1 |= CR1_PE_SET;
+       i2c->CR1 |= CR1_ACK_SET;
 }