--- /dev/null
+/**
+ * \file
+ * <!--
+ * This file is part of BeRTOS.
+ *
+ * Bertos is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * As a special exception, you may use this file as part of a free software
+ * library without restriction. Specifically, if other files instantiate
+ * templates or use macros or inline functions from this file, or you compile
+ * this file and link it with other files to produce an executable, this
+ * file does not by itself cause the resulting executable to be covered by
+ * the GNU General Public License. This exception does not however
+ * invalidate any other reasons why the executable file might be covered by
+ * the GNU General Public License.
+ *
+ * Copyright 2007 Develer S.r.l. (http://www.develer.com/)
+ *
+ * -->
+ *
+ * \brief Self programming routines.
+ *
+ * \version $Id$
+ * \author Francesco Sacchi <batt@develer.com>
+ * \author Daniele Basile <asterix@develer.com>
+ *
+ * This module implements a kfile-like access for Atmel avr
+ * internal flash.
+ * Internal flash writing access is controlled by BOOTSZ fuses, check
+ * datasheet for details.
+ */
+
+#include "flash_avr.h"
+
+#include <avr/io.h>
+#include <avr/boot.h>
+#include <avr/pgmspace.h>
+
+#include <cfg/macros.h> // MIN()
+#include <cfg/compiler.h>
+#include <cfg/debug.h>
+#include <cpu/cpu.h>
+
+#include <drv/wdt.h>
+
+#include <string.h>
+#include <stdio.h>
+
+typedef uint16_t avr_page_addr_t;
+typedef uint16_t avr_page_t;
+
+/**
+ * Temporary buffer cointaing data block to
+ * write on flash.
+ */
+static uint8_t page_buf[SPM_PAGESIZE];
+
+bool page_modified; /// Flag for checking if current page is modified.
+
+/**
+ * Current buffered page.
+ */
+static avr_page_t curr_page = 0;
+
+/**
+ * Write current buffered page in flash memory (if modified).
+ * This function erase flash memory page before writing.
+ */
+static void flash_avr_flush(void)
+{
+ if (page_modified)
+ {
+ kprintf("Flushing page %d\n", curr_page);
+
+ boot_spm_busy_wait(); // Wait while the SPM instruction is busy.
+
+ kprintf("Filling temparary page buffer...");
+ /* Fill the temporary buffer of the AVR */
+ for (avr_page_addr_t page_addr = 0; page_addr < SPM_PAGESIZE; page_addr += 2)
+ {
+ uint16_t word = ((uint16_t)page_buf[page_addr + 1] << 8) | page_buf[page_addr];
+
+ ATOMIC(boot_page_fill(page_addr, word));
+ }
+ kprintf("Done.\n");
+
+ wdt_reset();
+
+ kprintf("Erasing page, addr %u...", curr_page * SPM_PAGESIZE);
+
+ /* Page erase */
+ ATOMIC(boot_page_erase(curr_page * SPM_PAGESIZE));
+
+ /* Wait until the memory is erased. */
+ boot_spm_busy_wait();
+
+ kprintf("Done.\n");
+ kprintf("Writing page, addr %u...", curr_page * SPM_PAGESIZE);
+
+ /* Store buffer in flash page. */
+ ATOMIC(boot_page_write(curr_page * SPM_PAGESIZE));
+ boot_spm_busy_wait(); // Wait while the SPM instruction is busy.
+
+ /*
+ * Reenable RWW-section again. We need this if we want to jump back
+ * to the application after bootloading.
+ */
+ ATOMIC(boot_rww_enable());
+
+ page_modified = false;
+ kprintf("Done.\n");
+ }
+}
+
+
+/**
+ * Check current page and if \a page is different, load it in
+ * temporary buffer.
+ */
+static void flash_avr_loadPage(avr_page_t page)
+{
+ if (page != curr_page)
+ {
+ flash_avr_flush();
+ // Load page
+ memcpy_P(page_buf, (const char *)(page * SPM_PAGESIZE), SPM_PAGESIZE);
+ curr_page = page;
+ kprintf("Loaded page %d\n", curr_page);
+ }
+}
+
+/**
+ * Write program memory.
+ * Write \a size bytes from buffer \a _buf to file \a fd
+ * \note Write operations are buffered.
+ */
+static size_t flash_avr_write(struct _KFile *fd, const void *_buf, size_t size)
+{
+ const uint8_t *buf =(const uint8_t *)_buf;
+
+ avr_page_t page;
+ avr_page_addr_t page_addr;
+ size_t total_write = 0;
+
+ ASSERT(fd->seek_pos + size <= fd->size);
+ size = MIN((uint32_t)size, fd->size - fd->seek_pos);
+
+ kprintf("Writing at pos[%u]\n", fd->seek_pos);
+ while (size)
+ {
+ page = fd->seek_pos / SPM_PAGESIZE;
+ page_addr = fd->seek_pos % SPM_PAGESIZE;
+
+ flash_avr_loadPage(page);
+
+ size_t wr_len = MIN(size, SPM_PAGESIZE - page_addr);
+ memcpy(page_buf + page_addr, buf, wr_len);
+ page_modified = true;
+
+ buf += wr_len;
+ fd->seek_pos += wr_len;
+ size -= wr_len;
+ total_write += wr_len;
+ }
+ kprintf("written %u bytes\n", total_write);
+ return total_write;
+}
+
+/**
+ * Open flash file \a fd
+ * \a name and \a mode are unused, cause flash memory is
+ * threated like one file.
+ */
+static bool flash_avr_open(struct _KFile *fd, UNUSED_ARG(const char *, name), UNUSED_ARG(int, mode))
+{
+ curr_page = 0;
+ memcpy_P(page_buf, (const char *)(curr_page * SPM_PAGESIZE), SPM_PAGESIZE);
+
+ fd->seek_pos = 0;
+ fd->size = (uint16_t)(FLASHEND - CONFIG_BOOT_SIZE + 1);
+ page_modified = false;
+
+ kprintf("Flash file opened\n");
+ return true;
+}
+
+/**
+ * Close file \a fd
+ */
+static bool flash_avr_close(UNUSED_ARG(struct _KFile *,fd))
+{
+ flash_avr_flush();
+ kprintf("Flash file closed\n");
+ return true;
+}
+
+/**
+ * Move \a fd file seek position of \a offset bytes
+ * from current position.
+ */
+static int32_t flash_avr_seek(struct _KFile *fd, int32_t offset, KSeekMode whence)
+{
+ uint32_t seek_pos;
+
+ switch(whence)
+ {
+ case KSM_SEEK_SET:
+ seek_pos = 0;
+ break;
+ case KSM_SEEK_END:
+ seek_pos = fd->size - 1;
+ break;
+ case KSM_SEEK_CUR:
+ seek_pos = fd->seek_pos;
+ break;
+ default:
+ ASSERT(0);
+ return -1;
+ break;
+ }
+
+ /* Bound check */
+ if (seek_pos + offset > fd->size)
+ {
+ ASSERT(0);
+ return -1;
+ }
+
+ fd->seek_pos = seek_pos + offset;
+ kprintf("Flash seek to [%u]\n", fd->seek_pos);
+
+ return fd->seek_pos;
+}
+
+/**
+ * Read from file \a fd \a size bytes and put it in buffer \a buf
+ * \return the number of bytes read.
+ */
+static size_t flash_avr_read(struct _KFile *fd, void *buf, size_t size)
+{
+ ASSERT(fd->seek_pos + size <= fd->size);
+ size = MIN((uint32_t)size, fd->size - fd->seek_pos);
+
+ kprintf("Reading at pos[%u]\n", fd->seek_pos);
+ // Flush current buffered page (if modified).
+ flash_avr_flush();
+
+ /*
+ * AVR pointers are 16 bits wide, this hack is needed to avoid
+ * compiler warning, cause fd->seek_pos is a 32bit offset.
+ */
+ const uint8_t *pgm_addr = (const uint8_t *)0;
+ pgm_addr += fd->seek_pos;
+
+ memcpy_P(buf, pgm_addr, size);
+ fd->seek_pos += size;
+ kprintf("Read %u bytes\n", size);
+ return size;
+}
+
+/**
+ * Init AVR flash read/write file.
+ */
+void flash_avr_init(struct _KFile *fd)
+{
+ // Set up flash programming functions.
+ fd->open = flash_avr_open;
+ fd->close = flash_avr_close;
+ fd->read = flash_avr_read;
+ fd->write = flash_avr_write;
+ fd->seek = flash_avr_seek;
+}
+
+#if CONFIG_TEST
+
+#define TEST_SIZE 683
+#define ONE_BYTE_TEST_ADDRESS 347
+
+uint8_t test_buf[TEST_SIZE];
+uint8_t save_buf[TEST_SIZE];
+
+/**
+ * Program memory read/write subtest.
+ * Try to write/read in the same \a f file location \a _size bytes.
+ * \return true if all is ok, false otherwise
+ * \note Restore file position at exit (if no error)
+ * \note Test buffer \a buf must be filled with
+ * the following statement:
+ * <pre>
+ * buf[i] = i & 0xff
+ * </pre>
+ */
+static bool flash_avr_rwTest(KFile *f, uint8_t *buf, size_t _size)
+{
+ int32_t size = _size;
+ // Write test buffer
+ if (f->write(f, buf, size) != size)
+ return false;
+ f->seek(f, -size, SEEK_CUR);
+
+ // Reset test buffer
+ memset(buf, 0, size);
+
+ // Read flash in test buffer
+ if (f->read(f, buf, size) != size)
+ return false;
+ f->seek(f, -size, SEEK_CUR);
+
+ // Check test result
+ for (size_t i = 0; i < size; i++)
+ if (buf[i] != (i & 0xff))
+ return false;
+
+ return true;
+}
+
+/**
+ * Test for program memory read/write.
+ */
+bool flash_avr_test(void)
+{
+ KFile fd;
+
+ // Set up flash programming functions.
+ flash_avr_init(&fd);
+
+ // Fill in test buffer
+ for (int i = 0; i < TEST_SIZE; i++)
+ test_buf[i] = (i & 0xff);
+
+ // Open flash
+ fd.open(&fd, NULL, 0);
+ // Save flash content (for later restore).
+ fd.read(&fd, save_buf, sizeof(save_buf));
+ // Seek to addr 0
+ if (fd.seek(&fd, 0, SEEK_SET) != 0)
+ goto flash_avr_test_end;
+
+ // Test flash read/write to address 0..TEST_SIZE
+ if (!flash_avr_rwTest(&fd, test_buf, TEST_SIZE))
+ goto flash_avr_test_end;
+
+ // One byte read/write test
+ fd.seek(&fd, ONE_BYTE_TEST_ADDRESS, SEEK_CUR); // Random address
+ if (!flash_avr_rwTest(&fd, test_buf, 1))
+ goto flash_avr_test_end;
+ fd.seek(&fd, -(int32_t)ONE_BYTE_TEST_ADDRESS, SEEK_CUR);
+
+ // Restore old flash data
+ if (fd.write(&fd, save_buf, sizeof(test_buf)) != TEST_SIZE)
+ goto flash_avr_test_end;
+ fd.seek(&fd, -TEST_SIZE, SEEK_CUR);
+
+ // Go to the Flash end
+ fd.seek(&fd, -TEST_SIZE, SEEK_END);
+ // Save flash content (for later restore).
+ fd.read(&fd, save_buf, sizeof(save_buf));
+ fd.seek(&fd, -TEST_SIZE, SEEK_CUR);
+
+ // Test flash read/write to address (FLASHEND - TEST_SIZE) ... FLASHEND
+ if (!flash_avr_rwTest(&fd, test_buf, TEST_SIZE))
+ goto flash_avr_test_end;
+
+ // Go to half test size.
+ fd.seek(&fd, (TEST_SIZE / 2), SEEK_CUR);
+
+ // This test should FAIL, cause we try to write over file end.
+ kprintf("This test should fail.\n");
+ if (flash_avr_rwTest(&fd, test_buf, TEST_SIZE))
+ goto flash_avr_test_end;
+
+ fd.seek(&fd, -TEST_SIZE, SEEK_CUR);
+ // Restore old flash data
+ fd.write(&fd, save_buf, TEST_SIZE);
+
+ fd.close(&fd);
+ return true;
+
+flash_avr_test_end:
+ fd.close(&fd);
+ return false;
+}
+
+#endif
--- /dev/null
+/**
+ * \file
+ * <!--
+ * This file is part of BeRTOS.
+ *
+ * Bertos is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * As a special exception, you may use this file as part of a free software
+ * library without restriction. Specifically, if other files instantiate
+ * templates or use macros or inline functions from this file, or you compile
+ * this file and link it with other files to produce an executable, this
+ * file does not by itself cause the resulting executable to be covered by
+ * the GNU General Public License. This exception does not however
+ * invalidate any other reasons why the executable file might be covered by
+ * the GNU General Public License.
+ *
+ * Copyright 2007 Develer S.r.l. (http://www.develer.com/)
+ *
+ * -->
+ *
+ * \brief Self programming routines (interface).
+ *
+ * \version $Id$
+ * \author Francesco Sacchi <batt@develer.com>
+ * \author Daniele Basile <asterix@develer.com>
+ */
+
+#ifndef DRV_FLASH_AVR_H
+#define DRV_FLASH_AVR_H
+
+#include <cfg/compiler.h>
+#include <kern/kfile.h>
+
+bool flash_avr_test(void);
+void flash_avr_init(struct _KFile *fd);
+
+
+#endif /* DRV_FLASH_AVR_H */
--- /dev/null
+/**
+ * \file
+ * <!--
+ * This file is part of BeRTOS.
+ *
+ * Bertos is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * As a special exception, you may use this file as part of a free software
+ * library without restriction. Specifically, if other files instantiate
+ * templates or use macros or inline functions from this file, or you compile
+ * this file and link it with other files to produce an executable, this
+ * file does not by itself cause the resulting executable to be covered by
+ * the GNU General Public License. This exception does not however
+ * invalidate any other reasons why the executable file might be covered by
+ * the GNU General Public License.
+ *
+ * Copyright 2003, 2004 Develer S.r.l. (http://www.develer.com/)
+ * Copyright 2000 Bernardo Innocenti <bernie@codewiz.org>
+ *
+ * -->
+ *
+ * \brief AVR UART and SPI I/O driver
+ *
+ * Rationale for project_ks hardware.
+ *
+ * The serial 0 on the board_kf board is used to communicate with the
+ * smart card, which has the TX and RX lines connected together. To
+ * allow the smart card to drive the RX line of the CPU the CPU TX has
+ * to be in a high impedance state.
+ * Whenever a transmission is done and there is nothing more to send
+ * the transmitter is turn off. The output pin is held in input with
+ * pull-up enabled, to avoid capturing noise from the nearby RX line.
+ *
+ * The line on the KBus port must keep sending data, even when
+ * there is nothing to transmit, because a burst data transfer
+ * generates noise on the audio channels.
+ * This is accomplished using the multiprocessor mode of the
+ * ATmega64/128 serial.
+ *
+ * The receiver keeps the MPCM bit always on. When useful data
+ * is trasmitted the address bit is set. The receiver hardware
+ * consider the frame as address info and receive it.
+ * When useless fill bytes are sent the address bit is cleared
+ * and the receiver will ignore them, avoiding useless triggering
+ * of RXC interrupt.
+ *
+ * \version $Id$
+ * \author Bernardo Innocenti <bernie@develer.com>
+ * \author Stefano Fedrigo <aleph@develer.com>
+ */
+
+/*#*
+ *#* $Log$
+ *#* Revision 1.34 2006/11/23 13:19:02 batt
+ *#* Add support for ATmega1281.
+ *#*
+ *#* Revision 1.33 2006/09/13 18:21:24 bernie
+ *#* Add configurable SPI pin mapping.
+ *#*
+ *#* Revision 1.32 2006/07/19 12:56:26 bernie
+ *#* Convert to new Doxygen style.
+ *#*
+ *#* Revision 1.31 2006/05/18 00:37:29 bernie
+ *#* Use hw_ser.h instead of ubiquitous hw.h.
+ *#*
+ *#* Revision 1.30 2006/02/17 22:23:06 bernie
+ *#* Update POSIX serial emulator.
+ *#*
+ *#* Revision 1.29 2005/11/27 23:31:48 bernie
+ *#* Support avr-libc 1.4.
+ *#*
+ *#* Revision 1.28 2005/11/04 16:20:02 bernie
+ *#* Fix reference to README.devlib in header.
+ *#*
+ *#* Revision 1.27 2005/07/03 15:19:31 bernie
+ *#* Doxygen fix.
+ *#*
+ *#* Revision 1.26 2005/04/11 19:10:27 bernie
+ *#* Include top-level headers from cfg/ subdir.
+ *#*
+ *#* Revision 1.25 2005/01/25 08:37:26 bernie
+ *#* CONFIG_SER_HWHANDSHAKE fixes.
+ *#*
+ *#* Revision 1.24 2005/01/14 00:49:16 aleph
+ *#* Rename callbacks; SerialHardwareVT.txSending: New callback; Add SPI_BUS macros.
+ *#*
+ *#* Revision 1.23 2005/01/11 18:09:07 aleph
+ *#* Add ATmega8 SPI port definitions; Fix transmit complete IRQ bug; add strobe macros to uart1 and spi
+ *#*
+ *#* Revision 1.22 2004/12/31 17:47:45 bernie
+ *#* Rename UNUSED() to UNUSED_ARG().
+ *#*
+ *#* Revision 1.21 2004/12/13 12:07:06 bernie
+ *#* DISABLE_IRQSAVE/ENABLE_IRQRESTORE: Convert to IRQ_SAVE_DISABLE/IRQ_RESTORE.
+ *#*
+ *#* Revision 1.20 2004/12/13 11:51:43 bernie
+ *#* Fix a latent bug with reentrant serial IRQs.
+ *#*
+ *#* Revision 1.19 2004/12/13 11:51:08 bernie
+ *#* DISABLE_INTS/ENABLE_INTS: Convert to IRQ_DISABLE/IRQ_ENABLE.
+ *#*
+ *#* Revision 1.18 2004/12/08 08:03:48 bernie
+ *#* Doxygen fixes.
+ *#*
+ *#* Revision 1.17 2004/10/19 07:52:35 bernie
+ *#* Reset parity bits before overwriting them (Fixed by batt in project_ks).
+ *#*
+ *#* Revision 1.16 2004/10/03 18:45:48 bernie
+ *#* Convert to new-style config macros; Allow compiling with a C++ compiler (mostly).
+ *#*
+ *#* Revision 1.15 2004/09/14 21:05:36 bernie
+ *#* Use debug.h instead of kdebug.h; Use new AVR pin names; Spelling fixes.
+ *#*
+ *#* Revision 1.14 2004/09/06 21:50:00 bernie
+ *#* Spelling fixes.
+ *#*
+ *#* Revision 1.13 2004/09/06 21:40:50 bernie
+ *#* Move buffer handling in chip-specific driver.
+ *#*
+ *#* Revision 1.12 2004/08/29 22:06:10 bernie
+ *#* Fix a bug in the (unused) RTS/CTS code; Clarify documentation.
+ *#*
+ *#* Revision 1.10 2004/08/10 06:30:41 bernie
+ *#* Major redesign of serial bus policy handling.
+ *#*
+ *#* Revision 1.9 2004/08/02 20:20:29 aleph
+ *#* Merge from project_ks
+ *#*
+ *#* Revision 1.8 2004/07/29 22:57:09 bernie
+ *#* Several tweaks to reduce code size on ATmega8.
+ *#*
+ *#* Revision 1.7 2004/07/18 21:54:23 bernie
+ *#* Add ATmega8 support.
+ *#*
+ *#* Revision 1.5 2004/06/27 15:25:40 aleph
+ *#* Add missing callbacks for SPI;
+ *#* Change UNUSED() macro to new version with two args;
+ *#* Use TX line filling only on the correct KBUS serial port;
+ *#* Fix nasty IRQ disabling bug in recv complete hander for port 1.
+ *#*
+ *#* Revision 1.4 2004/06/03 11:27:09 bernie
+ *#* Add dual-license information.
+ *#*
+ *#* Revision 1.3 2004/06/02 21:35:24 aleph
+ *#* Serial enhancements: interruptible receive handler and 8 bit serial status for AVR; remove volatile attribute to FIFOBuffer, useless for new fifobuf routens
+ *#*
+ *#* Revision 1.2 2004/05/23 18:21:53 bernie
+ *#* Trim CVS logs and cleanup header info.
+ *#*
+ *#*/
+
+#include "ser.h"
+#include "ser_p.h"
+
+#include <hw_ser.h> /* Required for bus macros overrides */
+#include <hw_cpu.h> /* CLOCK_FREQ */
+#include <appconfig.h>
+
+#include <cfg/debug.h>
+#include <drv/timer.h>
+#include <mware/fifobuf.h>
+
+#include <avr/io.h>
+#if defined(__AVR_LIBC_VERSION__) && (__AVR_LIBC_VERSION__ >= 10400UL)
+ #include <avr/interrupt.h>
+#else
+ #include <avr/signal.h>
+#endif
+
+
+#if !CONFIG_SER_HWHANDSHAKE
+ /**
+ * \name Hardware handshake (RTS/CTS).
+ * \{
+ */
+ #define RTS_ON do {} while (0)
+ #define RTS_OFF do {} while (0)
+ #define IS_CTS_ON true
+ #define EIMSKF_CTS 0 /**< Dummy value, must be overridden */
+ /*\}*/
+#endif
+
+#if CPU_AVR_ATMEGA1281
+ #define BIT_RXCIE0 RXCIE0
+ #define BIT_RXEN0 RXEN0
+ #define BIT_TXEN0 TXEN0
+ #define BIT_UDRIE0 UDRIE0
+
+ #define BIT_RXCIE1 RXCIE1
+ #define BIT_RXEN1 RXEN1
+ #define BIT_TXEN1 TXEN1
+ #define BIT_UDRIE1 UDRIE1
+#else
+ #define BIT_RXCIE0 RXCIE
+ #define BIT_RXEN0 RXEN
+ #define BIT_TXEN0 TXEN
+ #define BIT_UDRIE0 UDRIE
+
+ #define BIT_RXCIE1 RXCIE
+ #define BIT_RXEN1 RXEN
+ #define BIT_TXEN1 TXEN
+ #define BIT_UDRIE1 UDRIE
+#endif
+
+
+/**
+ * \name Overridable serial bus hooks
+ *
+ * These can be redefined in hw.h to implement
+ * special bus policies such as half-duplex, 485, etc.
+ *
+ *
+ * \code
+ * TXBEGIN TXCHAR TXEND TXOFF
+ * | __________|__________ | |
+ * | | | | | | | | |
+ * v v v v v v v v v
+ * ______ __ __ __ __ __ __ ________________
+ * \/ \/ \/ \/ \/ \/ \/
+ * ______/\__/\__/\__/\__/\__/\__/
+ *
+ * \endcode
+ *
+ * \{
+ */
+#ifndef SER_UART0_BUS_TXINIT
+ /**
+ * Default TXINIT macro - invoked in uart0_init()
+ *
+ * - Enable both the receiver and the transmitter
+ * - Enable only the RX complete interrupt
+ */
+ #define SER_UART0_BUS_TXINIT do { \
+ UCSR0B = BV(BIT_RXCIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0); \
+ } while (0)
+#endif
+
+#ifndef SER_UART0_BUS_TXBEGIN
+ /**
+ * Invoked before starting a transmission
+ *
+ * - Enable both the receiver and the transmitter
+ * - Enable both the RX complete and UDR empty interrupts
+ */
+ #define SER_UART0_BUS_TXBEGIN do { \
+ UCSR0B = BV(BIT_RXCIE0) | BV(BIT_UDRIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0); \
+ } while (0)
+#endif
+
+#ifndef SER_UART0_BUS_TXCHAR
+ /**
+ * Invoked to send one character.
+ */
+ #define SER_UART0_BUS_TXCHAR(c) do { \
+ UDR0 = (c); \
+ } while (0)
+#endif
+
+#ifndef SER_UART0_BUS_TXEND
+ /**
+ * Invoked as soon as the txfifo becomes empty
+ *
+ * - Keep both the receiver and the transmitter enabled
+ * - Keep the RX complete interrupt enabled
+ * - Disable the UDR empty interrupt
+ */
+ #define SER_UART0_BUS_TXEND do { \
+ UCSR0B = BV(BIT_RXCIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0); \
+ } while (0)
+#endif
+
+#ifndef SER_UART0_BUS_TXOFF
+ /**
+ * \def SER_UART0_BUS_TXOFF
+ *
+ * Invoked after the last character has been transmitted
+ *
+ * The default is no action.
+ */
+ #ifdef __doxygen__
+ #define SER_UART0_BUS_TXOFF
+ #endif
+#endif
+
+#ifndef SER_UART1_BUS_TXINIT
+ /** \sa SER_UART0_BUS_TXINIT */
+ #define SER_UART1_BUS_TXINIT do { \
+ UCSR1B = BV(BIT_RXCIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1); \
+ } while (0)
+#endif
+#ifndef SER_UART1_BUS_TXBEGIN
+ /** \sa SER_UART0_BUS_TXBEGIN */
+ #define SER_UART1_BUS_TXBEGIN do { \
+ UCSR1B = BV(BIT_RXCIE1) | BV(BIT_UDRIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1); \
+ } while (0)
+#endif
+#ifndef SER_UART1_BUS_TXCHAR
+ /** \sa SER_UART0_BUS_TXCHAR */
+ #define SER_UART1_BUS_TXCHAR(c) do { \
+ UDR1 = (c); \
+ } while (0)
+#endif
+#ifndef SER_UART1_BUS_TXEND
+ /** \sa SER_UART0_BUS_TXEND */
+ #define SER_UART1_BUS_TXEND do { \
+ UCSR1B = BV(BIT_RXCIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1); \
+ } while (0)
+#endif
+#ifndef SER_UART1_BUS_TXOFF
+ /**
+ * \def SER_UART1_BUS_TXOFF
+ *
+ * \see SER_UART0_BUS_TXOFF
+ */
+ #ifdef __doxygen__
+ #define SER_UART1_BUS_TXOFF
+ #endif
+#endif
+/*\}*/
+
+
+/**
+ * \name Overridable SPI hooks
+ *
+ * These can be redefined in hw.h to implement
+ * special bus policies such as slave select pin handling, etc.
+ *
+ * \{
+ */
+#ifndef SER_SPI_BUS_TXINIT
+ /**
+ * Default TXINIT macro - invoked in spi_init()
+ * The default is no action.
+ */
+ #define SER_SPI_BUS_TXINIT
+#endif
+
+#ifndef SER_SPI_BUS_TXCLOSE
+ /**
+ * Invoked after the last character has been transmitted.
+ * The default is no action.
+ */
+ #define SER_SPI_BUS_TXCLOSE
+#endif
+/*\}*/
+
+
+/* SPI port and pin configuration */
+#if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103 || CPU_AVR_ATMEGA1281
+ #define SPI_PORT PORTB
+ #define SPI_DDR DDRB
+ #define SPI_SS_BIT PB0
+ #define SPI_SCK_BIT PB1
+ #define SPI_MOSI_BIT PB2
+ #define SPI_MISO_BIT PB3
+#elif CPU_AVR_ATMEGA8
+ #define SPI_PORT PORTB
+ #define SPI_DDR DDRB
+ #define SPI_SS_BIT PB2
+ #define SPI_SCK_BIT PB5
+ #define SPI_MOSI_BIT PB3
+ #define SPI_MISO_BIT PB4
+#else
+ #error Unknown architecture
+#endif
+
+/* USART register definitions */
+#if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA1281
+ #define AVR_HAS_UART1 1
+#elif CPU_AVR_ATMEGA8
+ #define AVR_HAS_UART1 0
+ #define UCSR0A UCSRA
+ #define UCSR0B UCSRB
+ #define UCSR0C UCSRC
+ #define UDR0 UDR
+ #define UBRR0L UBRRL
+ #define UBRR0H UBRRH
+ #define SIG_UART0_DATA SIG_UART_DATA
+ #define SIG_UART0_RECV SIG_UART_RECV
+ #define SIG_UART0_TRANS SIG_UART_TRANS
+#elif CPU_AVR_ATMEGA103
+ #define AVR_HAS_UART1 0
+ #define UCSR0B UCR
+ #define UDR0 UDR
+ #define UCSR0A USR
+ #define UBRR0L UBRR
+ #define SIG_UART0_DATA SIG_UART_DATA
+ #define SIG_UART0_RECV SIG_UART_RECV
+ #define SIG_UART0_TRANS SIG_UART_TRANS
+#else
+ #error Unknown architecture
+#endif
+
+
+/**
+ * \def CONFIG_SER_STROBE
+ *
+ * This is a debug facility that can be used to
+ * monitor SER interrupt activity on an external pin.
+ *
+ * To use strobes, redefine the macros SER_STROBE_ON,
+ * SER_STROBE_OFF and SER_STROBE_INIT and set
+ * CONFIG_SER_STROBE to 1.
+ */
+#if !defined(CONFIG_SER_STROBE) || !CONFIG_SER_STROBE
+ #define SER_STROBE_ON do {/*nop*/} while(0)
+ #define SER_STROBE_OFF do {/*nop*/} while(0)
+ #define SER_STROBE_INIT do {/*nop*/} while(0)
+#endif
+
+
+/* From the high-level serial driver */
+extern struct Serial ser_handles[SER_CNT];
+
+/* TX and RX buffers */
+static unsigned char uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
+static unsigned char uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
+#if AVR_HAS_UART1
+ static unsigned char uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
+ static unsigned char uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
+#endif
+static unsigned char spi_txbuffer[CONFIG_SPI_TXBUFSIZE];
+static unsigned char spi_rxbuffer[CONFIG_SPI_RXBUFSIZE];
+
+
+/**
+ * Internal hardware state structure
+ *
+ * The \a sending variable is true while the transmission
+ * interrupt is retriggering itself.
+ *
+ * For the USARTs the \a sending flag is useful for taking specific
+ * actions before sending a burst of data, at the start of a trasmission
+ * but not before every char sent.
+ *
+ * For the SPI, this flag is necessary because the SPI sends and receives
+ * bytes at the same time and the SPI IRQ is unique for send/receive.
+ * The only way to start transmission is to write data in SPDR (this
+ * is done by spi_starttx()). We do this *only* if a transfer is
+ * not already started.
+ */
+struct AvrSerial
+{
+ struct SerialHardware hw;
+ volatile bool sending;
+};
+
+
+/*
+ * These are to trick GCC into *not* using absolute addressing mode
+ * when accessing ser_handles, which is very expensive.
+ *
+ * Accessing through these pointers generates much shorter
+ * (and hopefully faster) code.
+ */
+struct Serial *ser_uart0 = &ser_handles[SER_UART0];
+#if AVR_HAS_UART1
+struct Serial *ser_uart1 = &ser_handles[SER_UART1];
+#endif
+struct Serial *ser_spi = &ser_handles[SER_SPI];
+
+
+
+/*
+ * Callbacks
+ */
+static void uart0_init(
+ UNUSED_ARG(struct SerialHardware *, _hw),
+ UNUSED_ARG(struct Serial *, ser))
+{
+ SER_UART0_BUS_TXINIT;
+ RTS_ON;
+ SER_STROBE_INIT;
+}
+
+static void uart0_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
+{
+ UCSR0B = 0;
+}
+
+static void uart0_enabletxirq(struct SerialHardware *_hw)
+{
+ struct AvrSerial *hw = (struct AvrSerial *)_hw;
+
+ /*
+ * WARNING: racy code here! The tx interrupt sets hw->sending to false
+ * when it runs with an empty fifo. The order of statements in the
+ * if-block matters.
+ */
+ if (!hw->sending)
+ {
+ hw->sending = true;
+ SER_UART0_BUS_TXBEGIN;
+ }
+}
+
+static void uart0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
+{
+ /* Compute baud-rate period */
+ uint16_t period = (((CLOCK_FREQ / 16UL) + (rate / 2)) / rate) - 1;
+
+#if !CPU_AVR_ATMEGA103
+ UBRR0H = (period) >> 8;
+#endif
+ UBRR0L = (period);
+
+ //DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);)
+}
+
+static void uart0_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
+{
+#if !CPU_AVR_ATMEGA103
+ UCSR0C = (UCSR0C & ~(BV(UPM01) | BV(UPM00))) | ((parity) << UPM00);
+#endif
+}
+
+#if AVR_HAS_UART1
+
+static void uart1_init(
+ UNUSED_ARG(struct SerialHardware *, _hw),
+ UNUSED_ARG(struct Serial *, ser))
+{
+ SER_UART1_BUS_TXINIT;
+ RTS_ON;
+ SER_STROBE_INIT;
+}
+
+static void uart1_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
+{
+ UCSR1B = 0;
+}
+
+static void uart1_enabletxirq(struct SerialHardware *_hw)
+{
+ struct AvrSerial *hw = (struct AvrSerial *)_hw;
+
+ /*
+ * WARNING: racy code here! The tx interrupt
+ * sets hw->sending to false when it runs with
+ * an empty fifo. The order of the statements
+ * in the if-block matters.
+ */
+ if (!hw->sending)
+ {
+ hw->sending = true;
+ SER_UART1_BUS_TXBEGIN;
+ }
+}
+
+static void uart1_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
+{
+ /* Compute baud-rate period */
+ uint16_t period = (((CLOCK_FREQ / 16UL) + (rate / 2)) / rate) - 1;
+
+ UBRR1H = (period) >> 8;
+ UBRR1L = (period);
+
+ //DB(kprintf("uart1_setbaudrate(rate=%ld): period=%d\n", rate, period);)
+}
+
+static void uart1_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
+{
+ UCSR1C = (UCSR1C & ~(BV(UPM11) | BV(UPM10))) | ((parity) << UPM10);
+}
+
+#endif // AVR_HAS_UART1
+
+static void spi_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct Serial *, ser))
+{
+ /*
+ * Set MOSI and SCK ports out, MISO in.
+ *
+ * The ATmega64/128 datasheet explicitly states that the input/output
+ * state of the SPI pins is not significant, as when the SPI is
+ * active the I/O port are overrided.
+ * This is *blatantly FALSE*.
+ *
+ * Moreover, the MISO pin on the board_kc *must* be in high impedance
+ * state even when the SPI is off, because the line is wired together
+ * with the KBus serial RX, and the transmitter of the slave boards
+ * would be unable to drive the line.
+ */
+ ATOMIC(SPI_DDR |= (BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT)));
+
+ /*
+ * If the SPI master mode is activated and the SS pin is in input and tied low,
+ * the SPI hardware will automatically switch to slave mode!
+ * For proper communication this pins should therefore be:
+ * - as output
+ * - as input but tied high forever!
+ * This driver set the pin as output.
+ */
+ #warning SPI SS pin set as output for proper operation, check schematics for possible conflicts.
+ ATOMIC(SPI_DDR |= BV(SPI_SS_BIT));
+
+ ATOMIC(SPI_DDR &= ~BV(SPI_MISO_BIT));
+ /* Enable SPI, IRQ on, Master */
+ SPCR = BV(SPE) | BV(SPIE) | BV(MSTR);
+
+ /* Set data order */
+ #if CONFIG_SPI_DATA_ORDER == SER_LSB_FIRST
+ SPCR |= BV(DORD);
+ #endif
+
+ /* Set SPI clock rate */
+ #if CONFIG_SPI_CLOCK_DIV == 128
+ SPCR |= (BV(SPR1) | BV(SPR0));
+ #elif (CONFIG_SPI_CLOCK_DIV == 64 || CONFIG_SPI_CLOCK_DIV == 32)
+ SPCR |= BV(SPR1);
+ #elif (CONFIG_SPI_CLOCK_DIV == 16 || CONFIG_SPI_CLOCK_DIV == 8)
+ SPCR |= BV(SPR0);
+ #elif (CONFIG_SPI_CLOCK_DIV == 4 || CONFIG_SPI_CLOCK_DIV == 2)
+ // SPR0 & SDPR1 both at 0
+ #else
+ #error Unsupported SPI clock division factor.
+ #endif
+
+ /* Set SPI2X bit (spi double frequency) */
+ #if (CONFIG_SPI_CLOCK_DIV == 128 || CONFIG_SPI_CLOCK_DIV == 64 \
+ || CONFIG_SPI_CLOCK_DIV == 16 || CONFIG_SPI_CLOCK_DIV == 4)
+ SPSR &= ~BV(SPI2X);
+ #elif (CONFIG_SPI_CLOCK_DIV == 32 || CONFIG_SPI_CLOCK_DIV == 8 || CONFIG_SPI_CLOCK_DIV == 2)
+ SPSR |= BV(SPI2X);
+ #else
+ #error Unsupported SPI clock division factor.
+ #endif
+
+ /* Set clock polarity */
+ #if CONFIG_SPI_CLOCK_POL == 1
+ SPCR |= BV(CPOL);
+ #endif
+
+ /* Set clock phase */
+ #if CONFIG_SPI_CLOCK_PHASE == 1
+ SPCR |= BV(CPHA);
+ #endif
+ SER_SPI_BUS_TXINIT;
+
+ SER_STROBE_INIT;
+}
+
+static void spi_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
+{
+ SPCR = 0;
+
+ SER_SPI_BUS_TXCLOSE;
+
+ /* Set all pins as inputs */
+ ATOMIC(SPI_DDR &= ~(BV(SPI_MISO_BIT) | BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT) | BV(SPI_SS_BIT)));
+}
+
+static void spi_starttx(struct SerialHardware *_hw)
+{
+ struct AvrSerial *hw = (struct AvrSerial *)_hw;
+
+ cpuflags_t flags;
+ IRQ_SAVE_DISABLE(flags);
+
+ /* Send data only if the SPI is not already transmitting */
+ if (!hw->sending && !fifo_isempty(&ser_spi->txfifo))
+ {
+ hw->sending = true;
+ SPDR = fifo_pop(&ser_spi->txfifo);
+ }
+
+ IRQ_RESTORE(flags);
+}
+
+static void spi_setbaudrate(
+ UNUSED_ARG(struct SerialHardware *, _hw),
+ UNUSED_ARG(unsigned long, rate))
+{
+ // nop
+}
+
+static void spi_setparity(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(int, parity))
+{
+ // nop
+}
+
+static bool tx_sending(struct SerialHardware* _hw)
+{
+ struct AvrSerial *hw = (struct AvrSerial *)_hw;
+ return hw->sending;
+}
+
+
+
+// FIXME: move into compiler.h? Ditch?
+#if COMPILER_C99
+ #define C99INIT(name,val) .name = val
+#elif defined(__GNUC__)
+ #define C99INIT(name,val) name: val
+#else
+ #warning No designated initializers, double check your code
+ #define C99INIT(name,val) (val)
+#endif
+
+/*
+ * High-level interface data structures
+ */
+static const struct SerialHardwareVT UART0_VT =
+{
+ C99INIT(init, uart0_init),
+ C99INIT(cleanup, uart0_cleanup),
+ C99INIT(setBaudrate, uart0_setbaudrate),
+ C99INIT(setParity, uart0_setparity),
+ C99INIT(txStart, uart0_enabletxirq),
+ C99INIT(txSending, tx_sending),
+};
+
+#if AVR_HAS_UART1
+static const struct SerialHardwareVT UART1_VT =
+{
+ C99INIT(init, uart1_init),
+ C99INIT(cleanup, uart1_cleanup),
+ C99INIT(setBaudrate, uart1_setbaudrate),
+ C99INIT(setParity, uart1_setparity),
+ C99INIT(txStart, uart1_enabletxirq),
+ C99INIT(txSending, tx_sending),
+};
+#endif // AVR_HAS_UART1
+
+static const struct SerialHardwareVT SPI_VT =
+{
+ C99INIT(init, spi_init),
+ C99INIT(cleanup, spi_cleanup),
+ C99INIT(setBaudrate, spi_setbaudrate),
+ C99INIT(setParity, spi_setparity),
+ C99INIT(txStart, spi_starttx),
+ C99INIT(txSending, tx_sending),
+};
+
+static struct AvrSerial UARTDescs[SER_CNT] =
+{
+ {
+ C99INIT(hw, /**/) {
+ C99INIT(table, &UART0_VT),
+ C99INIT(txbuffer, uart0_txbuffer),
+ C99INIT(rxbuffer, uart0_rxbuffer),
+ C99INIT(txbuffer_size, sizeof(uart0_txbuffer)),
+ C99INIT(rxbuffer_size, sizeof(uart0_rxbuffer)),
+ },
+ C99INIT(sending, false),
+ },
+#if AVR_HAS_UART1
+ {
+ C99INIT(hw, /**/) {
+ C99INIT(table, &UART1_VT),
+ C99INIT(txbuffer, uart1_txbuffer),
+ C99INIT(rxbuffer, uart1_rxbuffer),
+ C99INIT(txbuffer_size, sizeof(uart1_txbuffer)),
+ C99INIT(rxbuffer_size, sizeof(uart1_rxbuffer)),
+ },
+ C99INIT(sending, false),
+ },
+#endif
+ {
+ C99INIT(hw, /**/) {
+ C99INIT(table, &SPI_VT),
+ C99INIT(txbuffer, spi_txbuffer),
+ C99INIT(rxbuffer, spi_rxbuffer),
+ C99INIT(txbuffer_size, sizeof(spi_txbuffer)),
+ C99INIT(rxbuffer_size, sizeof(spi_rxbuffer)),
+ },
+ C99INIT(sending, false),
+ }
+};
+
+struct SerialHardware *ser_hw_getdesc(int unit)
+{
+ ASSERT(unit < SER_CNT);
+ return &UARTDescs[unit].hw;
+}
+
+
+/*
+ * Interrupt handlers
+ */
+
+#if CONFIG_SER_HWHANDSHAKE
+
+/// This interrupt is triggered when the CTS line goes high
+SIGNAL(SIG_CTS)
+{
+ // Re-enable UDR empty interrupt and TX, then disable CTS interrupt
+ UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
+ EIMSK &= ~EIMSKF_CTS;
+}
+
+#endif // CONFIG_SER_HWHANDSHAKE
+
+
+/**
+ * Serial 0 TX interrupt handler
+ */
+SIGNAL(USART0_UDRE_vect)
+{
+ SER_STROBE_ON;
+
+ struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
+
+ if (fifo_isempty(txfifo))
+ {
+ SER_UART0_BUS_TXEND;
+#ifndef SER_UART0_BUS_TXOFF
+ UARTDescs[SER_UART0].sending = false;
+#endif
+ }
+#if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
+ else if (!IS_CTS_ON)
+ {
+ // Disable rx interrupt and tx, enable CTS interrupt
+ // UNTESTED
+ UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN);
+ EIFR |= EIMSKF_CTS;
+ EIMSK |= EIMSKF_CTS;
+ }
+#endif
+ else
+ {
+ char c = fifo_pop(txfifo);
+ SER_UART0_BUS_TXCHAR(c);
+ }
+
+ SER_STROBE_OFF;
+}
+
+#ifdef SER_UART0_BUS_TXOFF
+/**
+ * Serial port 0 TX complete interrupt handler.
+ *
+ * This IRQ is usually disabled. The UDR-empty interrupt
+ * enables it when there's no more data to transmit.
+ * We need to wait until the last character has been
+ * transmitted before switching the 485 transceiver to
+ * receive mode.
+ *
+ * The txfifo might have been refilled by putchar() while
+ * we were waiting for the transmission complete interrupt.
+ * In this case, we must restart the UDR empty interrupt,
+ * otherwise we'd stop the serial port with some data
+ * still pending in the buffer.
+ */
+SIGNAL(SIG_UART0_TRANS)
+{
+ SER_STROBE_ON;
+
+ struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
+ if (fifo_isempty(txfifo))
+ {
+ SER_UART0_BUS_TXOFF;
+ UARTDescs[SER_UART0].sending = false;
+ }
+ else
+ UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
+
+ SER_STROBE_OFF;
+}
+#endif /* SER_UART0_BUS_TXOFF */
+
+
+#if AVR_HAS_UART1
+
+/**
+ * Serial 1 TX interrupt handler
+ */
+SIGNAL(USART1_UDRE_vect)
+{
+ SER_STROBE_ON;
+
+ struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
+
+ if (fifo_isempty(txfifo))
+ {
+ SER_UART1_BUS_TXEND;
+#ifndef SER_UART1_BUS_TXOFF
+ UARTDescs[SER_UART1].sending = false;
+#endif
+ }
+#if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
+ else if (!IS_CTS_ON)
+ {
+ // Disable rx interrupt and tx, enable CTS interrupt
+ // UNTESTED
+ UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN);
+ EIFR |= EIMSKF_CTS;
+ EIMSK |= EIMSKF_CTS;
+ }
+#endif
+ else
+ {
+ char c = fifo_pop(txfifo);
+ SER_UART1_BUS_TXCHAR(c);
+ }
+
+ SER_STROBE_OFF;
+}
+
+#ifdef SER_UART1_BUS_TXOFF
+/**
+ * Serial port 1 TX complete interrupt handler.
+ *
+ * \sa port 0 TX complete handler.
+ */
+SIGNAL(SIG_UART1_TRANS)
+{
+ SER_STROBE_ON;
+
+ struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
+ if (fifo_isempty(txfifo))
+ {
+ SER_UART1_BUS_TXOFF;
+ UARTDescs[SER_UART1].sending = false;
+ }
+ else
+ UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
+
+ SER_STROBE_OFF;
+}
+#endif /* SER_UART1_BUS_TXOFF */
+
+#endif // AVR_HAS_UART1
+
+
+/**
+ * Serial 0 RX complete interrupt handler.
+ *
+ * This handler is interruptible.
+ * Interrupt are reenabled as soon as recv complete interrupt is
+ * disabled. Using INTERRUPT() is troublesome when the serial
+ * is heavily loaded, because an interrupt could be retriggered
+ * when executing the handler prologue before RXCIE is disabled.
+ *
+ * \note The code that re-enables interrupts is commented out
+ * because in some nasty cases the interrupt is retriggered.
+ * This is probably due to the RXC flag being set before
+ * RXCIE is cleared. Unfortunately the RXC flag is read-only
+ * and can't be cleared by code.
+ */
+SIGNAL(USART0_RX_vect)
+{
+ SER_STROBE_ON;
+
+ /* Disable Recv complete IRQ */
+ //UCSR0B &= ~BV(RXCIE);
+ //IRQ_ENABLE;
+
+ /* Should be read before UDR */
+ ser_uart0->status |= UCSR0A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
+
+ /* To clear the RXC flag we must _always_ read the UDR even when we're
+ * not going to accept the incoming data, otherwise a new interrupt
+ * will occur once the handler terminates.
+ */
+ char c = UDR0;
+ struct FIFOBuffer * const rxfifo = &ser_uart0->rxfifo;
+
+ if (fifo_isfull(rxfifo))
+ ser_uart0->status |= SERRF_RXFIFOOVERRUN;
+ else
+ {
+ fifo_push(rxfifo, c);
+#if CONFIG_SER_HWHANDSHAKE
+ if (fifo_isfull(rxfifo))
+ RTS_OFF;
+#endif
+ }
+
+ /* Reenable receive complete int */
+ //IRQ_DISABLE;
+ //UCSR0B |= BV(RXCIE);
+
+ SER_STROBE_OFF;
+}
+
+
+#if AVR_HAS_UART1
+
+/**
+ * Serial 1 RX complete interrupt handler.
+ *
+ * This handler is interruptible.
+ * Interrupt are reenabled as soon as recv complete interrupt is
+ * disabled. Using INTERRUPT() is troublesome when the serial
+ * is heavily loaded, because an interrupt could be retriggered
+ * when executing the handler prologue before RXCIE is disabled.
+ *
+ * \see SIGNAL(USART1_RX_vect)
+ */
+SIGNAL(USART1_RX_vect)
+{
+ SER_STROBE_ON;
+
+ /* Disable Recv complete IRQ */
+ //UCSR1B &= ~BV(RXCIE);
+ //IRQ_ENABLE;
+
+ /* Should be read before UDR */
+ ser_uart1->status |= UCSR1A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
+
+ /* To avoid an IRQ storm, we must _always_ read the UDR even when we're
+ * not going to accept the incoming data
+ */
+ char c = UDR1;
+ struct FIFOBuffer * const rxfifo = &ser_uart1->rxfifo;
+ //ASSERT_VALID_FIFO(rxfifo);
+
+ if (UNLIKELY(fifo_isfull(rxfifo)))
+ ser_uart1->status |= SERRF_RXFIFOOVERRUN;
+ else
+ {
+ fifo_push(rxfifo, c);
+#if CONFIG_SER_HWHANDSHAKE
+ if (fifo_isfull(rxfifo))
+ RTS_OFF;
+#endif
+ }
+ /* Re-enable receive complete int */
+ //IRQ_DISABLE;
+ //UCSR1B |= BV(RXCIE);
+
+ SER_STROBE_OFF;
+}
+
+#endif // AVR_HAS_UART1
+
+
+/**
+ * SPI interrupt handler
+ */
+SIGNAL(SIG_SPI)
+{
+ SER_STROBE_ON;
+
+ /* Read incoming byte. */
+ if (!fifo_isfull(&ser_spi->rxfifo))
+ fifo_push(&ser_spi->rxfifo, SPDR);
+ /*
+ * FIXME
+ else
+ ser_spi->status |= SERRF_RXFIFOOVERRUN;
+ */
+
+ /* Send */
+ if (!fifo_isempty(&ser_spi->txfifo))
+ SPDR = fifo_pop(&ser_spi->txfifo);
+ else
+ UARTDescs[SER_SPI].sending = false;
+
+ SER_STROBE_OFF;
+}
+++ /dev/null
-/**
- * \file
- * <!--
- * This file is part of BeRTOS.
- *
- * Bertos is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- *
- * As a special exception, you may use this file as part of a free software
- * library without restriction. Specifically, if other files instantiate
- * templates or use macros or inline functions from this file, or you compile
- * this file and link it with other files to produce an executable, this
- * file does not by itself cause the resulting executable to be covered by
- * the GNU General Public License. This exception does not however
- * invalidate any other reasons why the executable file might be covered by
- * the GNU General Public License.
- *
- * Copyright 2007 Develer S.r.l. (http://www.develer.com/)
- *
- * -->
- *
- * \brief Self programming routines.
- *
- * \version $Id$
- * \author Francesco Sacchi <batt@develer.com>
- * \author Daniele Basile <asterix@develer.com>
- *
- * This module implements a kfile-like access for Atmel avr
- * internal flash.
- * Internal flash writing access is controlled by BOOTSZ fuses, check
- * datasheet for details.
- */
-
-#include "flash_avr.h"
-
-#include <avr/io.h>
-#include <avr/boot.h>
-#include <avr/pgmspace.h>
-
-#include <cfg/macros.h> // MIN()
-#include <cfg/compiler.h>
-#include <cfg/debug.h>
-#include <cpu/cpu.h>
-
-#include <drv/wdt.h>
-
-#include <string.h>
-#include <stdio.h>
-
-typedef uint16_t avr_page_addr_t;
-typedef uint16_t avr_page_t;
-
-/**
- * Temporary buffer cointaing data block to
- * write on flash.
- */
-static uint8_t page_buf[SPM_PAGESIZE];
-
-bool page_modified; /// Flag for checking if current page is modified.
-
-/**
- * Current buffered page.
- */
-static avr_page_t curr_page = 0;
-
-/**
- * Write current buffered page in flash memory (if modified).
- * This function erase flash memory page before writing.
- */
-static void flash_avr_flush(void)
-{
- if (page_modified)
- {
- kprintf("Flushing page %d\n", curr_page);
-
- boot_spm_busy_wait(); // Wait while the SPM instruction is busy.
-
- kprintf("Filling temparary page buffer...");
- /* Fill the temporary buffer of the AVR */
- for (avr_page_addr_t page_addr = 0; page_addr < SPM_PAGESIZE; page_addr += 2)
- {
- uint16_t word = ((uint16_t)page_buf[page_addr + 1] << 8) | page_buf[page_addr];
-
- ATOMIC(boot_page_fill(page_addr, word));
- }
- kprintf("Done.\n");
-
- wdt_reset();
-
- kprintf("Erasing page, addr %u...", curr_page * SPM_PAGESIZE);
-
- /* Page erase */
- ATOMIC(boot_page_erase(curr_page * SPM_PAGESIZE));
-
- /* Wait until the memory is erased. */
- boot_spm_busy_wait();
-
- kprintf("Done.\n");
- kprintf("Writing page, addr %u...", curr_page * SPM_PAGESIZE);
-
- /* Store buffer in flash page. */
- ATOMIC(boot_page_write(curr_page * SPM_PAGESIZE));
- boot_spm_busy_wait(); // Wait while the SPM instruction is busy.
-
- /*
- * Reenable RWW-section again. We need this if we want to jump back
- * to the application after bootloading.
- */
- ATOMIC(boot_rww_enable());
-
- page_modified = false;
- kprintf("Done.\n");
- }
-}
-
-
-/**
- * Check current page and if \a page is different, load it in
- * temporary buffer.
- */
-static void flash_avr_loadPage(avr_page_t page)
-{
- if (page != curr_page)
- {
- flash_avr_flush();
- // Load page
- memcpy_P(page_buf, (const char *)(page * SPM_PAGESIZE), SPM_PAGESIZE);
- curr_page = page;
- kprintf("Loaded page %d\n", curr_page);
- }
-}
-
-/**
- * Write program memory.
- * Write \a size bytes from buffer \a _buf to file \a fd
- * \note Write operations are buffered.
- */
-static size_t flash_avr_write(struct _KFile *fd, const void *_buf, size_t size)
-{
- const uint8_t *buf =(const uint8_t *)_buf;
-
- avr_page_t page;
- avr_page_addr_t page_addr;
- size_t total_write = 0;
-
- ASSERT(fd->seek_pos + size <= fd->size);
- size = MIN((uint32_t)size, fd->size - fd->seek_pos);
-
- kprintf("Writing at pos[%u]\n", fd->seek_pos);
- while (size)
- {
- page = fd->seek_pos / SPM_PAGESIZE;
- page_addr = fd->seek_pos % SPM_PAGESIZE;
-
- flash_avr_loadPage(page);
-
- size_t wr_len = MIN(size, SPM_PAGESIZE - page_addr);
- memcpy(page_buf + page_addr, buf, wr_len);
- page_modified = true;
-
- buf += wr_len;
- fd->seek_pos += wr_len;
- size -= wr_len;
- total_write += wr_len;
- }
- kprintf("written %u bytes\n", total_write);
- return total_write;
-}
-
-/**
- * Open flash file \a fd
- * \a name and \a mode are unused, cause flash memory is
- * threated like one file.
- */
-static bool flash_avr_open(struct _KFile *fd, UNUSED_ARG(const char *, name), UNUSED_ARG(int, mode))
-{
- curr_page = 0;
- memcpy_P(page_buf, (const char *)(curr_page * SPM_PAGESIZE), SPM_PAGESIZE);
-
- fd->seek_pos = 0;
- fd->size = (uint16_t)(FLASHEND - CONFIG_BOOT_SIZE + 1);
- page_modified = false;
-
- kprintf("Flash file opened\n");
- return true;
-}
-
-/**
- * Close file \a fd
- */
-static bool flash_avr_close(UNUSED_ARG(struct _KFile *,fd))
-{
- flash_avr_flush();
- kprintf("Flash file closed\n");
- return true;
-}
-
-/**
- * Move \a fd file seek position of \a offset bytes
- * from current position.
- */
-static int32_t flash_avr_seek(struct _KFile *fd, int32_t offset, KSeekMode whence)
-{
- uint32_t seek_pos;
-
- switch(whence)
- {
- case KSM_SEEK_SET:
- seek_pos = 0;
- break;
- case KSM_SEEK_END:
- seek_pos = fd->size - 1;
- break;
- case KSM_SEEK_CUR:
- seek_pos = fd->seek_pos;
- break;
- default:
- ASSERT(0);
- return -1;
- break;
- }
-
- /* Bound check */
- if (seek_pos + offset > fd->size)
- {
- ASSERT(0);
- return -1;
- }
-
- fd->seek_pos = seek_pos + offset;
- kprintf("Flash seek to [%u]\n", fd->seek_pos);
-
- return fd->seek_pos;
-}
-
-/**
- * Read from file \a fd \a size bytes and put it in buffer \a buf
- * \return the number of bytes read.
- */
-static size_t flash_avr_read(struct _KFile *fd, void *buf, size_t size)
-{
- ASSERT(fd->seek_pos + size <= fd->size);
- size = MIN((uint32_t)size, fd->size - fd->seek_pos);
-
- kprintf("Reading at pos[%u]\n", fd->seek_pos);
- // Flush current buffered page (if modified).
- flash_avr_flush();
-
- /*
- * AVR pointers are 16 bits wide, this hack is needed to avoid
- * compiler warning, cause fd->seek_pos is a 32bit offset.
- */
- const uint8_t *pgm_addr = (const uint8_t *)0;
- pgm_addr += fd->seek_pos;
-
- memcpy_P(buf, pgm_addr, size);
- fd->seek_pos += size;
- kprintf("Read %u bytes\n", size);
- return size;
-}
-
-/**
- * Init AVR flash read/write file.
- */
-void flash_avr_init(struct _KFile *fd)
-{
- // Set up flash programming functions.
- fd->open = flash_avr_open;
- fd->close = flash_avr_close;
- fd->read = flash_avr_read;
- fd->write = flash_avr_write;
- fd->seek = flash_avr_seek;
-}
-
-#if CONFIG_TEST
-
-#define TEST_SIZE 683
-#define ONE_BYTE_TEST_ADDRESS 347
-
-uint8_t test_buf[TEST_SIZE];
-uint8_t save_buf[TEST_SIZE];
-
-/**
- * Program memory read/write subtest.
- * Try to write/read in the same \a f file location \a _size bytes.
- * \return true if all is ok, false otherwise
- * \note Restore file position at exit (if no error)
- * \note Test buffer \a buf must be filled with
- * the following statement:
- * <pre>
- * buf[i] = i & 0xff
- * </pre>
- */
-static bool flash_avr_rwTest(KFile *f, uint8_t *buf, size_t _size)
-{
- int32_t size = _size;
- // Write test buffer
- if (f->write(f, buf, size) != size)
- return false;
- f->seek(f, -size, SEEK_CUR);
-
- // Reset test buffer
- memset(buf, 0, size);
-
- // Read flash in test buffer
- if (f->read(f, buf, size) != size)
- return false;
- f->seek(f, -size, SEEK_CUR);
-
- // Check test result
- for (size_t i = 0; i < size; i++)
- if (buf[i] != (i & 0xff))
- return false;
-
- return true;
-}
-
-/**
- * Test for program memory read/write.
- */
-bool flash_avr_test(void)
-{
- KFile fd;
-
- // Set up flash programming functions.
- flash_avr_init(&fd);
-
- // Fill in test buffer
- for (int i = 0; i < TEST_SIZE; i++)
- test_buf[i] = (i & 0xff);
-
- // Open flash
- fd.open(&fd, NULL, 0);
- // Save flash content (for later restore).
- fd.read(&fd, save_buf, sizeof(save_buf));
- // Seek to addr 0
- if (fd.seek(&fd, 0, SEEK_SET) != 0)
- goto flash_avr_test_end;
-
- // Test flash read/write to address 0..TEST_SIZE
- if (!flash_avr_rwTest(&fd, test_buf, TEST_SIZE))
- goto flash_avr_test_end;
-
- // One byte read/write test
- fd.seek(&fd, ONE_BYTE_TEST_ADDRESS, SEEK_CUR); // Random address
- if (!flash_avr_rwTest(&fd, test_buf, 1))
- goto flash_avr_test_end;
- fd.seek(&fd, -(int32_t)ONE_BYTE_TEST_ADDRESS, SEEK_CUR);
-
- // Restore old flash data
- if (fd.write(&fd, save_buf, sizeof(test_buf)) != TEST_SIZE)
- goto flash_avr_test_end;
- fd.seek(&fd, -TEST_SIZE, SEEK_CUR);
-
- // Go to the Flash end
- fd.seek(&fd, -TEST_SIZE, SEEK_END);
- // Save flash content (for later restore).
- fd.read(&fd, save_buf, sizeof(save_buf));
- fd.seek(&fd, -TEST_SIZE, SEEK_CUR);
-
- // Test flash read/write to address (FLASHEND - TEST_SIZE) ... FLASHEND
- if (!flash_avr_rwTest(&fd, test_buf, TEST_SIZE))
- goto flash_avr_test_end;
-
- // Go to half test size.
- fd.seek(&fd, (TEST_SIZE / 2), SEEK_CUR);
-
- // This test should FAIL, cause we try to write over file end.
- kprintf("This test should fail.\n");
- if (flash_avr_rwTest(&fd, test_buf, TEST_SIZE))
- goto flash_avr_test_end;
-
- fd.seek(&fd, -TEST_SIZE, SEEK_CUR);
- // Restore old flash data
- fd.write(&fd, save_buf, TEST_SIZE);
-
- fd.close(&fd);
- return true;
-
-flash_avr_test_end:
- fd.close(&fd);
- return false;
-}
-
-#endif
+++ /dev/null
-/**
- * \file
- * <!--
- * This file is part of BeRTOS.
- *
- * Bertos is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- *
- * As a special exception, you may use this file as part of a free software
- * library without restriction. Specifically, if other files instantiate
- * templates or use macros or inline functions from this file, or you compile
- * this file and link it with other files to produce an executable, this
- * file does not by itself cause the resulting executable to be covered by
- * the GNU General Public License. This exception does not however
- * invalidate any other reasons why the executable file might be covered by
- * the GNU General Public License.
- *
- * Copyright 2007 Develer S.r.l. (http://www.develer.com/)
- *
- * -->
- *
- * \brief Self programming routines (interface).
- *
- * \version $Id$
- * \author Francesco Sacchi <batt@develer.com>
- * \author Daniele Basile <asterix@develer.com>
- */
-
-#ifndef DRV_FLASH_AVR_H
-#define DRV_FLASH_AVR_H
-
-#include <cfg/compiler.h>
-#include <kern/kfile.h>
-
-bool flash_avr_test(void);
-void flash_avr_init(struct _KFile *fd);
-
-
-#endif /* DRV_FLASH_AVR_H */
+++ /dev/null
-/**
- * \file
- * <!--
- * This file is part of BeRTOS.
- *
- * Bertos is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- *
- * As a special exception, you may use this file as part of a free software
- * library without restriction. Specifically, if other files instantiate
- * templates or use macros or inline functions from this file, or you compile
- * this file and link it with other files to produce an executable, this
- * file does not by itself cause the resulting executable to be covered by
- * the GNU General Public License. This exception does not however
- * invalidate any other reasons why the executable file might be covered by
- * the GNU General Public License.
- *
- * Copyright 2003, 2004 Develer S.r.l. (http://www.develer.com/)
- * Copyright 2000 Bernardo Innocenti <bernie@codewiz.org>
- *
- * -->
- *
- * \brief AVR UART and SPI I/O driver
- *
- * Rationale for project_ks hardware.
- *
- * The serial 0 on the board_kf board is used to communicate with the
- * smart card, which has the TX and RX lines connected together. To
- * allow the smart card to drive the RX line of the CPU the CPU TX has
- * to be in a high impedance state.
- * Whenever a transmission is done and there is nothing more to send
- * the transmitter is turn off. The output pin is held in input with
- * pull-up enabled, to avoid capturing noise from the nearby RX line.
- *
- * The line on the KBus port must keep sending data, even when
- * there is nothing to transmit, because a burst data transfer
- * generates noise on the audio channels.
- * This is accomplished using the multiprocessor mode of the
- * ATmega64/128 serial.
- *
- * The receiver keeps the MPCM bit always on. When useful data
- * is trasmitted the address bit is set. The receiver hardware
- * consider the frame as address info and receive it.
- * When useless fill bytes are sent the address bit is cleared
- * and the receiver will ignore them, avoiding useless triggering
- * of RXC interrupt.
- *
- * \version $Id$
- * \author Bernardo Innocenti <bernie@develer.com>
- * \author Stefano Fedrigo <aleph@develer.com>
- */
-
-/*#*
- *#* $Log$
- *#* Revision 1.34 2006/11/23 13:19:02 batt
- *#* Add support for ATmega1281.
- *#*
- *#* Revision 1.33 2006/09/13 18:21:24 bernie
- *#* Add configurable SPI pin mapping.
- *#*
- *#* Revision 1.32 2006/07/19 12:56:26 bernie
- *#* Convert to new Doxygen style.
- *#*
- *#* Revision 1.31 2006/05/18 00:37:29 bernie
- *#* Use hw_ser.h instead of ubiquitous hw.h.
- *#*
- *#* Revision 1.30 2006/02/17 22:23:06 bernie
- *#* Update POSIX serial emulator.
- *#*
- *#* Revision 1.29 2005/11/27 23:31:48 bernie
- *#* Support avr-libc 1.4.
- *#*
- *#* Revision 1.28 2005/11/04 16:20:02 bernie
- *#* Fix reference to README.devlib in header.
- *#*
- *#* Revision 1.27 2005/07/03 15:19:31 bernie
- *#* Doxygen fix.
- *#*
- *#* Revision 1.26 2005/04/11 19:10:27 bernie
- *#* Include top-level headers from cfg/ subdir.
- *#*
- *#* Revision 1.25 2005/01/25 08:37:26 bernie
- *#* CONFIG_SER_HWHANDSHAKE fixes.
- *#*
- *#* Revision 1.24 2005/01/14 00:49:16 aleph
- *#* Rename callbacks; SerialHardwareVT.txSending: New callback; Add SPI_BUS macros.
- *#*
- *#* Revision 1.23 2005/01/11 18:09:07 aleph
- *#* Add ATmega8 SPI port definitions; Fix transmit complete IRQ bug; add strobe macros to uart1 and spi
- *#*
- *#* Revision 1.22 2004/12/31 17:47:45 bernie
- *#* Rename UNUSED() to UNUSED_ARG().
- *#*
- *#* Revision 1.21 2004/12/13 12:07:06 bernie
- *#* DISABLE_IRQSAVE/ENABLE_IRQRESTORE: Convert to IRQ_SAVE_DISABLE/IRQ_RESTORE.
- *#*
- *#* Revision 1.20 2004/12/13 11:51:43 bernie
- *#* Fix a latent bug with reentrant serial IRQs.
- *#*
- *#* Revision 1.19 2004/12/13 11:51:08 bernie
- *#* DISABLE_INTS/ENABLE_INTS: Convert to IRQ_DISABLE/IRQ_ENABLE.
- *#*
- *#* Revision 1.18 2004/12/08 08:03:48 bernie
- *#* Doxygen fixes.
- *#*
- *#* Revision 1.17 2004/10/19 07:52:35 bernie
- *#* Reset parity bits before overwriting them (Fixed by batt in project_ks).
- *#*
- *#* Revision 1.16 2004/10/03 18:45:48 bernie
- *#* Convert to new-style config macros; Allow compiling with a C++ compiler (mostly).
- *#*
- *#* Revision 1.15 2004/09/14 21:05:36 bernie
- *#* Use debug.h instead of kdebug.h; Use new AVR pin names; Spelling fixes.
- *#*
- *#* Revision 1.14 2004/09/06 21:50:00 bernie
- *#* Spelling fixes.
- *#*
- *#* Revision 1.13 2004/09/06 21:40:50 bernie
- *#* Move buffer handling in chip-specific driver.
- *#*
- *#* Revision 1.12 2004/08/29 22:06:10 bernie
- *#* Fix a bug in the (unused) RTS/CTS code; Clarify documentation.
- *#*
- *#* Revision 1.10 2004/08/10 06:30:41 bernie
- *#* Major redesign of serial bus policy handling.
- *#*
- *#* Revision 1.9 2004/08/02 20:20:29 aleph
- *#* Merge from project_ks
- *#*
- *#* Revision 1.8 2004/07/29 22:57:09 bernie
- *#* Several tweaks to reduce code size on ATmega8.
- *#*
- *#* Revision 1.7 2004/07/18 21:54:23 bernie
- *#* Add ATmega8 support.
- *#*
- *#* Revision 1.5 2004/06/27 15:25:40 aleph
- *#* Add missing callbacks for SPI;
- *#* Change UNUSED() macro to new version with two args;
- *#* Use TX line filling only on the correct KBUS serial port;
- *#* Fix nasty IRQ disabling bug in recv complete hander for port 1.
- *#*
- *#* Revision 1.4 2004/06/03 11:27:09 bernie
- *#* Add dual-license information.
- *#*
- *#* Revision 1.3 2004/06/02 21:35:24 aleph
- *#* Serial enhancements: interruptible receive handler and 8 bit serial status for AVR; remove volatile attribute to FIFOBuffer, useless for new fifobuf routens
- *#*
- *#* Revision 1.2 2004/05/23 18:21:53 bernie
- *#* Trim CVS logs and cleanup header info.
- *#*
- *#*/
-
-#include "ser.h"
-#include "ser_p.h"
-
-#include <hw_ser.h> /* Required for bus macros overrides */
-#include <hw_cpu.h> /* CLOCK_FREQ */
-#include <appconfig.h>
-
-#include <cfg/debug.h>
-#include <drv/timer.h>
-#include <mware/fifobuf.h>
-
-#include <avr/io.h>
-#if defined(__AVR_LIBC_VERSION__) && (__AVR_LIBC_VERSION__ >= 10400UL)
- #include <avr/interrupt.h>
-#else
- #include <avr/signal.h>
-#endif
-
-
-#if !CONFIG_SER_HWHANDSHAKE
- /**
- * \name Hardware handshake (RTS/CTS).
- * \{
- */
- #define RTS_ON do {} while (0)
- #define RTS_OFF do {} while (0)
- #define IS_CTS_ON true
- #define EIMSKF_CTS 0 /**< Dummy value, must be overridden */
- /*\}*/
-#endif
-
-#if CPU_AVR_ATMEGA1281
- #define BIT_RXCIE0 RXCIE0
- #define BIT_RXEN0 RXEN0
- #define BIT_TXEN0 TXEN0
- #define BIT_UDRIE0 UDRIE0
-
- #define BIT_RXCIE1 RXCIE1
- #define BIT_RXEN1 RXEN1
- #define BIT_TXEN1 TXEN1
- #define BIT_UDRIE1 UDRIE1
-#else
- #define BIT_RXCIE0 RXCIE
- #define BIT_RXEN0 RXEN
- #define BIT_TXEN0 TXEN
- #define BIT_UDRIE0 UDRIE
-
- #define BIT_RXCIE1 RXCIE
- #define BIT_RXEN1 RXEN
- #define BIT_TXEN1 TXEN
- #define BIT_UDRIE1 UDRIE
-#endif
-
-
-/**
- * \name Overridable serial bus hooks
- *
- * These can be redefined in hw.h to implement
- * special bus policies such as half-duplex, 485, etc.
- *
- *
- * \code
- * TXBEGIN TXCHAR TXEND TXOFF
- * | __________|__________ | |
- * | | | | | | | | |
- * v v v v v v v v v
- * ______ __ __ __ __ __ __ ________________
- * \/ \/ \/ \/ \/ \/ \/
- * ______/\__/\__/\__/\__/\__/\__/
- *
- * \endcode
- *
- * \{
- */
-#ifndef SER_UART0_BUS_TXINIT
- /**
- * Default TXINIT macro - invoked in uart0_init()
- *
- * - Enable both the receiver and the transmitter
- * - Enable only the RX complete interrupt
- */
- #define SER_UART0_BUS_TXINIT do { \
- UCSR0B = BV(BIT_RXCIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0); \
- } while (0)
-#endif
-
-#ifndef SER_UART0_BUS_TXBEGIN
- /**
- * Invoked before starting a transmission
- *
- * - Enable both the receiver and the transmitter
- * - Enable both the RX complete and UDR empty interrupts
- */
- #define SER_UART0_BUS_TXBEGIN do { \
- UCSR0B = BV(BIT_RXCIE0) | BV(BIT_UDRIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0); \
- } while (0)
-#endif
-
-#ifndef SER_UART0_BUS_TXCHAR
- /**
- * Invoked to send one character.
- */
- #define SER_UART0_BUS_TXCHAR(c) do { \
- UDR0 = (c); \
- } while (0)
-#endif
-
-#ifndef SER_UART0_BUS_TXEND
- /**
- * Invoked as soon as the txfifo becomes empty
- *
- * - Keep both the receiver and the transmitter enabled
- * - Keep the RX complete interrupt enabled
- * - Disable the UDR empty interrupt
- */
- #define SER_UART0_BUS_TXEND do { \
- UCSR0B = BV(BIT_RXCIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0); \
- } while (0)
-#endif
-
-#ifndef SER_UART0_BUS_TXOFF
- /**
- * \def SER_UART0_BUS_TXOFF
- *
- * Invoked after the last character has been transmitted
- *
- * The default is no action.
- */
- #ifdef __doxygen__
- #define SER_UART0_BUS_TXOFF
- #endif
-#endif
-
-#ifndef SER_UART1_BUS_TXINIT
- /** \sa SER_UART0_BUS_TXINIT */
- #define SER_UART1_BUS_TXINIT do { \
- UCSR1B = BV(BIT_RXCIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1); \
- } while (0)
-#endif
-#ifndef SER_UART1_BUS_TXBEGIN
- /** \sa SER_UART0_BUS_TXBEGIN */
- #define SER_UART1_BUS_TXBEGIN do { \
- UCSR1B = BV(BIT_RXCIE1) | BV(BIT_UDRIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1); \
- } while (0)
-#endif
-#ifndef SER_UART1_BUS_TXCHAR
- /** \sa SER_UART0_BUS_TXCHAR */
- #define SER_UART1_BUS_TXCHAR(c) do { \
- UDR1 = (c); \
- } while (0)
-#endif
-#ifndef SER_UART1_BUS_TXEND
- /** \sa SER_UART0_BUS_TXEND */
- #define SER_UART1_BUS_TXEND do { \
- UCSR1B = BV(BIT_RXCIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1); \
- } while (0)
-#endif
-#ifndef SER_UART1_BUS_TXOFF
- /**
- * \def SER_UART1_BUS_TXOFF
- *
- * \see SER_UART0_BUS_TXOFF
- */
- #ifdef __doxygen__
- #define SER_UART1_BUS_TXOFF
- #endif
-#endif
-/*\}*/
-
-
-/**
- * \name Overridable SPI hooks
- *
- * These can be redefined in hw.h to implement
- * special bus policies such as slave select pin handling, etc.
- *
- * \{
- */
-#ifndef SER_SPI_BUS_TXINIT
- /**
- * Default TXINIT macro - invoked in spi_init()
- * The default is no action.
- */
- #define SER_SPI_BUS_TXINIT
-#endif
-
-#ifndef SER_SPI_BUS_TXCLOSE
- /**
- * Invoked after the last character has been transmitted.
- * The default is no action.
- */
- #define SER_SPI_BUS_TXCLOSE
-#endif
-/*\}*/
-
-
-/* SPI port and pin configuration */
-#if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103 || CPU_AVR_ATMEGA1281
- #define SPI_PORT PORTB
- #define SPI_DDR DDRB
- #define SPI_SS_BIT PB0
- #define SPI_SCK_BIT PB1
- #define SPI_MOSI_BIT PB2
- #define SPI_MISO_BIT PB3
-#elif CPU_AVR_ATMEGA8
- #define SPI_PORT PORTB
- #define SPI_DDR DDRB
- #define SPI_SS_BIT PB2
- #define SPI_SCK_BIT PB5
- #define SPI_MOSI_BIT PB3
- #define SPI_MISO_BIT PB4
-#else
- #error Unknown architecture
-#endif
-
-/* USART register definitions */
-#if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA1281
- #define AVR_HAS_UART1 1
-#elif CPU_AVR_ATMEGA8
- #define AVR_HAS_UART1 0
- #define UCSR0A UCSRA
- #define UCSR0B UCSRB
- #define UCSR0C UCSRC
- #define UDR0 UDR
- #define UBRR0L UBRRL
- #define UBRR0H UBRRH
- #define SIG_UART0_DATA SIG_UART_DATA
- #define SIG_UART0_RECV SIG_UART_RECV
- #define SIG_UART0_TRANS SIG_UART_TRANS
-#elif CPU_AVR_ATMEGA103
- #define AVR_HAS_UART1 0
- #define UCSR0B UCR
- #define UDR0 UDR
- #define UCSR0A USR
- #define UBRR0L UBRR
- #define SIG_UART0_DATA SIG_UART_DATA
- #define SIG_UART0_RECV SIG_UART_RECV
- #define SIG_UART0_TRANS SIG_UART_TRANS
-#else
- #error Unknown architecture
-#endif
-
-
-/**
- * \def CONFIG_SER_STROBE
- *
- * This is a debug facility that can be used to
- * monitor SER interrupt activity on an external pin.
- *
- * To use strobes, redefine the macros SER_STROBE_ON,
- * SER_STROBE_OFF and SER_STROBE_INIT and set
- * CONFIG_SER_STROBE to 1.
- */
-#if !defined(CONFIG_SER_STROBE) || !CONFIG_SER_STROBE
- #define SER_STROBE_ON do {/*nop*/} while(0)
- #define SER_STROBE_OFF do {/*nop*/} while(0)
- #define SER_STROBE_INIT do {/*nop*/} while(0)
-#endif
-
-
-/* From the high-level serial driver */
-extern struct Serial ser_handles[SER_CNT];
-
-/* TX and RX buffers */
-static unsigned char uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
-static unsigned char uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
-#if AVR_HAS_UART1
- static unsigned char uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
- static unsigned char uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
-#endif
-static unsigned char spi_txbuffer[CONFIG_SPI_TXBUFSIZE];
-static unsigned char spi_rxbuffer[CONFIG_SPI_RXBUFSIZE];
-
-
-/**
- * Internal hardware state structure
- *
- * The \a sending variable is true while the transmission
- * interrupt is retriggering itself.
- *
- * For the USARTs the \a sending flag is useful for taking specific
- * actions before sending a burst of data, at the start of a trasmission
- * but not before every char sent.
- *
- * For the SPI, this flag is necessary because the SPI sends and receives
- * bytes at the same time and the SPI IRQ is unique for send/receive.
- * The only way to start transmission is to write data in SPDR (this
- * is done by spi_starttx()). We do this *only* if a transfer is
- * not already started.
- */
-struct AvrSerial
-{
- struct SerialHardware hw;
- volatile bool sending;
-};
-
-
-/*
- * These are to trick GCC into *not* using absolute addressing mode
- * when accessing ser_handles, which is very expensive.
- *
- * Accessing through these pointers generates much shorter
- * (and hopefully faster) code.
- */
-struct Serial *ser_uart0 = &ser_handles[SER_UART0];
-#if AVR_HAS_UART1
-struct Serial *ser_uart1 = &ser_handles[SER_UART1];
-#endif
-struct Serial *ser_spi = &ser_handles[SER_SPI];
-
-
-
-/*
- * Callbacks
- */
-static void uart0_init(
- UNUSED_ARG(struct SerialHardware *, _hw),
- UNUSED_ARG(struct Serial *, ser))
-{
- SER_UART0_BUS_TXINIT;
- RTS_ON;
- SER_STROBE_INIT;
-}
-
-static void uart0_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
-{
- UCSR0B = 0;
-}
-
-static void uart0_enabletxirq(struct SerialHardware *_hw)
-{
- struct AvrSerial *hw = (struct AvrSerial *)_hw;
-
- /*
- * WARNING: racy code here! The tx interrupt sets hw->sending to false
- * when it runs with an empty fifo. The order of statements in the
- * if-block matters.
- */
- if (!hw->sending)
- {
- hw->sending = true;
- SER_UART0_BUS_TXBEGIN;
- }
-}
-
-static void uart0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
-{
- /* Compute baud-rate period */
- uint16_t period = (((CLOCK_FREQ / 16UL) + (rate / 2)) / rate) - 1;
-
-#if !CPU_AVR_ATMEGA103
- UBRR0H = (period) >> 8;
-#endif
- UBRR0L = (period);
-
- //DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);)
-}
-
-static void uart0_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
-{
-#if !CPU_AVR_ATMEGA103
- UCSR0C = (UCSR0C & ~(BV(UPM01) | BV(UPM00))) | ((parity) << UPM00);
-#endif
-}
-
-#if AVR_HAS_UART1
-
-static void uart1_init(
- UNUSED_ARG(struct SerialHardware *, _hw),
- UNUSED_ARG(struct Serial *, ser))
-{
- SER_UART1_BUS_TXINIT;
- RTS_ON;
- SER_STROBE_INIT;
-}
-
-static void uart1_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
-{
- UCSR1B = 0;
-}
-
-static void uart1_enabletxirq(struct SerialHardware *_hw)
-{
- struct AvrSerial *hw = (struct AvrSerial *)_hw;
-
- /*
- * WARNING: racy code here! The tx interrupt
- * sets hw->sending to false when it runs with
- * an empty fifo. The order of the statements
- * in the if-block matters.
- */
- if (!hw->sending)
- {
- hw->sending = true;
- SER_UART1_BUS_TXBEGIN;
- }
-}
-
-static void uart1_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
-{
- /* Compute baud-rate period */
- uint16_t period = (((CLOCK_FREQ / 16UL) + (rate / 2)) / rate) - 1;
-
- UBRR1H = (period) >> 8;
- UBRR1L = (period);
-
- //DB(kprintf("uart1_setbaudrate(rate=%ld): period=%d\n", rate, period);)
-}
-
-static void uart1_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
-{
- UCSR1C = (UCSR1C & ~(BV(UPM11) | BV(UPM10))) | ((parity) << UPM10);
-}
-
-#endif // AVR_HAS_UART1
-
-static void spi_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct Serial *, ser))
-{
- /*
- * Set MOSI and SCK ports out, MISO in.
- *
- * The ATmega64/128 datasheet explicitly states that the input/output
- * state of the SPI pins is not significant, as when the SPI is
- * active the I/O port are overrided.
- * This is *blatantly FALSE*.
- *
- * Moreover, the MISO pin on the board_kc *must* be in high impedance
- * state even when the SPI is off, because the line is wired together
- * with the KBus serial RX, and the transmitter of the slave boards
- * would be unable to drive the line.
- */
- ATOMIC(SPI_DDR |= (BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT)));
-
- /*
- * If the SPI master mode is activated and the SS pin is in input and tied low,
- * the SPI hardware will automatically switch to slave mode!
- * For proper communication this pins should therefore be:
- * - as output
- * - as input but tied high forever!
- * This driver set the pin as output.
- */
- #warning SPI SS pin set as output for proper operation, check schematics for possible conflicts.
- ATOMIC(SPI_DDR |= BV(SPI_SS_BIT));
-
- ATOMIC(SPI_DDR &= ~BV(SPI_MISO_BIT));
- /* Enable SPI, IRQ on, Master */
- SPCR = BV(SPE) | BV(SPIE) | BV(MSTR);
-
- /* Set data order */
- #if CONFIG_SPI_DATA_ORDER == SER_LSB_FIRST
- SPCR |= BV(DORD);
- #endif
-
- /* Set SPI clock rate */
- #if CONFIG_SPI_CLOCK_DIV == 128
- SPCR |= (BV(SPR1) | BV(SPR0));
- #elif (CONFIG_SPI_CLOCK_DIV == 64 || CONFIG_SPI_CLOCK_DIV == 32)
- SPCR |= BV(SPR1);
- #elif (CONFIG_SPI_CLOCK_DIV == 16 || CONFIG_SPI_CLOCK_DIV == 8)
- SPCR |= BV(SPR0);
- #elif (CONFIG_SPI_CLOCK_DIV == 4 || CONFIG_SPI_CLOCK_DIV == 2)
- // SPR0 & SDPR1 both at 0
- #else
- #error Unsupported SPI clock division factor.
- #endif
-
- /* Set SPI2X bit (spi double frequency) */
- #if (CONFIG_SPI_CLOCK_DIV == 128 || CONFIG_SPI_CLOCK_DIV == 64 \
- || CONFIG_SPI_CLOCK_DIV == 16 || CONFIG_SPI_CLOCK_DIV == 4)
- SPSR &= ~BV(SPI2X);
- #elif (CONFIG_SPI_CLOCK_DIV == 32 || CONFIG_SPI_CLOCK_DIV == 8 || CONFIG_SPI_CLOCK_DIV == 2)
- SPSR |= BV(SPI2X);
- #else
- #error Unsupported SPI clock division factor.
- #endif
-
- /* Set clock polarity */
- #if CONFIG_SPI_CLOCK_POL == 1
- SPCR |= BV(CPOL);
- #endif
-
- /* Set clock phase */
- #if CONFIG_SPI_CLOCK_PHASE == 1
- SPCR |= BV(CPHA);
- #endif
- SER_SPI_BUS_TXINIT;
-
- SER_STROBE_INIT;
-}
-
-static void spi_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
-{
- SPCR = 0;
-
- SER_SPI_BUS_TXCLOSE;
-
- /* Set all pins as inputs */
- ATOMIC(SPI_DDR &= ~(BV(SPI_MISO_BIT) | BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT) | BV(SPI_SS_BIT)));
-}
-
-static void spi_starttx(struct SerialHardware *_hw)
-{
- struct AvrSerial *hw = (struct AvrSerial *)_hw;
-
- cpuflags_t flags;
- IRQ_SAVE_DISABLE(flags);
-
- /* Send data only if the SPI is not already transmitting */
- if (!hw->sending && !fifo_isempty(&ser_spi->txfifo))
- {
- hw->sending = true;
- SPDR = fifo_pop(&ser_spi->txfifo);
- }
-
- IRQ_RESTORE(flags);
-}
-
-static void spi_setbaudrate(
- UNUSED_ARG(struct SerialHardware *, _hw),
- UNUSED_ARG(unsigned long, rate))
-{
- // nop
-}
-
-static void spi_setparity(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(int, parity))
-{
- // nop
-}
-
-static bool tx_sending(struct SerialHardware* _hw)
-{
- struct AvrSerial *hw = (struct AvrSerial *)_hw;
- return hw->sending;
-}
-
-
-
-// FIXME: move into compiler.h? Ditch?
-#if COMPILER_C99
- #define C99INIT(name,val) .name = val
-#elif defined(__GNUC__)
- #define C99INIT(name,val) name: val
-#else
- #warning No designated initializers, double check your code
- #define C99INIT(name,val) (val)
-#endif
-
-/*
- * High-level interface data structures
- */
-static const struct SerialHardwareVT UART0_VT =
-{
- C99INIT(init, uart0_init),
- C99INIT(cleanup, uart0_cleanup),
- C99INIT(setBaudrate, uart0_setbaudrate),
- C99INIT(setParity, uart0_setparity),
- C99INIT(txStart, uart0_enabletxirq),
- C99INIT(txSending, tx_sending),
-};
-
-#if AVR_HAS_UART1
-static const struct SerialHardwareVT UART1_VT =
-{
- C99INIT(init, uart1_init),
- C99INIT(cleanup, uart1_cleanup),
- C99INIT(setBaudrate, uart1_setbaudrate),
- C99INIT(setParity, uart1_setparity),
- C99INIT(txStart, uart1_enabletxirq),
- C99INIT(txSending, tx_sending),
-};
-#endif // AVR_HAS_UART1
-
-static const struct SerialHardwareVT SPI_VT =
-{
- C99INIT(init, spi_init),
- C99INIT(cleanup, spi_cleanup),
- C99INIT(setBaudrate, spi_setbaudrate),
- C99INIT(setParity, spi_setparity),
- C99INIT(txStart, spi_starttx),
- C99INIT(txSending, tx_sending),
-};
-
-static struct AvrSerial UARTDescs[SER_CNT] =
-{
- {
- C99INIT(hw, /**/) {
- C99INIT(table, &UART0_VT),
- C99INIT(txbuffer, uart0_txbuffer),
- C99INIT(rxbuffer, uart0_rxbuffer),
- C99INIT(txbuffer_size, sizeof(uart0_txbuffer)),
- C99INIT(rxbuffer_size, sizeof(uart0_rxbuffer)),
- },
- C99INIT(sending, false),
- },
-#if AVR_HAS_UART1
- {
- C99INIT(hw, /**/) {
- C99INIT(table, &UART1_VT),
- C99INIT(txbuffer, uart1_txbuffer),
- C99INIT(rxbuffer, uart1_rxbuffer),
- C99INIT(txbuffer_size, sizeof(uart1_txbuffer)),
- C99INIT(rxbuffer_size, sizeof(uart1_rxbuffer)),
- },
- C99INIT(sending, false),
- },
-#endif
- {
- C99INIT(hw, /**/) {
- C99INIT(table, &SPI_VT),
- C99INIT(txbuffer, spi_txbuffer),
- C99INIT(rxbuffer, spi_rxbuffer),
- C99INIT(txbuffer_size, sizeof(spi_txbuffer)),
- C99INIT(rxbuffer_size, sizeof(spi_rxbuffer)),
- },
- C99INIT(sending, false),
- }
-};
-
-struct SerialHardware *ser_hw_getdesc(int unit)
-{
- ASSERT(unit < SER_CNT);
- return &UARTDescs[unit].hw;
-}
-
-
-/*
- * Interrupt handlers
- */
-
-#if CONFIG_SER_HWHANDSHAKE
-
-/// This interrupt is triggered when the CTS line goes high
-SIGNAL(SIG_CTS)
-{
- // Re-enable UDR empty interrupt and TX, then disable CTS interrupt
- UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
- EIMSK &= ~EIMSKF_CTS;
-}
-
-#endif // CONFIG_SER_HWHANDSHAKE
-
-
-/**
- * Serial 0 TX interrupt handler
- */
-SIGNAL(USART0_UDRE_vect)
-{
- SER_STROBE_ON;
-
- struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
-
- if (fifo_isempty(txfifo))
- {
- SER_UART0_BUS_TXEND;
-#ifndef SER_UART0_BUS_TXOFF
- UARTDescs[SER_UART0].sending = false;
-#endif
- }
-#if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
- else if (!IS_CTS_ON)
- {
- // Disable rx interrupt and tx, enable CTS interrupt
- // UNTESTED
- UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN);
- EIFR |= EIMSKF_CTS;
- EIMSK |= EIMSKF_CTS;
- }
-#endif
- else
- {
- char c = fifo_pop(txfifo);
- SER_UART0_BUS_TXCHAR(c);
- }
-
- SER_STROBE_OFF;
-}
-
-#ifdef SER_UART0_BUS_TXOFF
-/**
- * Serial port 0 TX complete interrupt handler.
- *
- * This IRQ is usually disabled. The UDR-empty interrupt
- * enables it when there's no more data to transmit.
- * We need to wait until the last character has been
- * transmitted before switching the 485 transceiver to
- * receive mode.
- *
- * The txfifo might have been refilled by putchar() while
- * we were waiting for the transmission complete interrupt.
- * In this case, we must restart the UDR empty interrupt,
- * otherwise we'd stop the serial port with some data
- * still pending in the buffer.
- */
-SIGNAL(SIG_UART0_TRANS)
-{
- SER_STROBE_ON;
-
- struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
- if (fifo_isempty(txfifo))
- {
- SER_UART0_BUS_TXOFF;
- UARTDescs[SER_UART0].sending = false;
- }
- else
- UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
-
- SER_STROBE_OFF;
-}
-#endif /* SER_UART0_BUS_TXOFF */
-
-
-#if AVR_HAS_UART1
-
-/**
- * Serial 1 TX interrupt handler
- */
-SIGNAL(USART1_UDRE_vect)
-{
- SER_STROBE_ON;
-
- struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
-
- if (fifo_isempty(txfifo))
- {
- SER_UART1_BUS_TXEND;
-#ifndef SER_UART1_BUS_TXOFF
- UARTDescs[SER_UART1].sending = false;
-#endif
- }
-#if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
- else if (!IS_CTS_ON)
- {
- // Disable rx interrupt and tx, enable CTS interrupt
- // UNTESTED
- UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN);
- EIFR |= EIMSKF_CTS;
- EIMSK |= EIMSKF_CTS;
- }
-#endif
- else
- {
- char c = fifo_pop(txfifo);
- SER_UART1_BUS_TXCHAR(c);
- }
-
- SER_STROBE_OFF;
-}
-
-#ifdef SER_UART1_BUS_TXOFF
-/**
- * Serial port 1 TX complete interrupt handler.
- *
- * \sa port 0 TX complete handler.
- */
-SIGNAL(SIG_UART1_TRANS)
-{
- SER_STROBE_ON;
-
- struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
- if (fifo_isempty(txfifo))
- {
- SER_UART1_BUS_TXOFF;
- UARTDescs[SER_UART1].sending = false;
- }
- else
- UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
-
- SER_STROBE_OFF;
-}
-#endif /* SER_UART1_BUS_TXOFF */
-
-#endif // AVR_HAS_UART1
-
-
-/**
- * Serial 0 RX complete interrupt handler.
- *
- * This handler is interruptible.
- * Interrupt are reenabled as soon as recv complete interrupt is
- * disabled. Using INTERRUPT() is troublesome when the serial
- * is heavily loaded, because an interrupt could be retriggered
- * when executing the handler prologue before RXCIE is disabled.
- *
- * \note The code that re-enables interrupts is commented out
- * because in some nasty cases the interrupt is retriggered.
- * This is probably due to the RXC flag being set before
- * RXCIE is cleared. Unfortunately the RXC flag is read-only
- * and can't be cleared by code.
- */
-SIGNAL(USART0_RX_vect)
-{
- SER_STROBE_ON;
-
- /* Disable Recv complete IRQ */
- //UCSR0B &= ~BV(RXCIE);
- //IRQ_ENABLE;
-
- /* Should be read before UDR */
- ser_uart0->status |= UCSR0A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
-
- /* To clear the RXC flag we must _always_ read the UDR even when we're
- * not going to accept the incoming data, otherwise a new interrupt
- * will occur once the handler terminates.
- */
- char c = UDR0;
- struct FIFOBuffer * const rxfifo = &ser_uart0->rxfifo;
-
- if (fifo_isfull(rxfifo))
- ser_uart0->status |= SERRF_RXFIFOOVERRUN;
- else
- {
- fifo_push(rxfifo, c);
-#if CONFIG_SER_HWHANDSHAKE
- if (fifo_isfull(rxfifo))
- RTS_OFF;
-#endif
- }
-
- /* Reenable receive complete int */
- //IRQ_DISABLE;
- //UCSR0B |= BV(RXCIE);
-
- SER_STROBE_OFF;
-}
-
-
-#if AVR_HAS_UART1
-
-/**
- * Serial 1 RX complete interrupt handler.
- *
- * This handler is interruptible.
- * Interrupt are reenabled as soon as recv complete interrupt is
- * disabled. Using INTERRUPT() is troublesome when the serial
- * is heavily loaded, because an interrupt could be retriggered
- * when executing the handler prologue before RXCIE is disabled.
- *
- * \see SIGNAL(USART1_RX_vect)
- */
-SIGNAL(USART1_RX_vect)
-{
- SER_STROBE_ON;
-
- /* Disable Recv complete IRQ */
- //UCSR1B &= ~BV(RXCIE);
- //IRQ_ENABLE;
-
- /* Should be read before UDR */
- ser_uart1->status |= UCSR1A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
-
- /* To avoid an IRQ storm, we must _always_ read the UDR even when we're
- * not going to accept the incoming data
- */
- char c = UDR1;
- struct FIFOBuffer * const rxfifo = &ser_uart1->rxfifo;
- //ASSERT_VALID_FIFO(rxfifo);
-
- if (UNLIKELY(fifo_isfull(rxfifo)))
- ser_uart1->status |= SERRF_RXFIFOOVERRUN;
- else
- {
- fifo_push(rxfifo, c);
-#if CONFIG_SER_HWHANDSHAKE
- if (fifo_isfull(rxfifo))
- RTS_OFF;
-#endif
- }
- /* Re-enable receive complete int */
- //IRQ_DISABLE;
- //UCSR1B |= BV(RXCIE);
-
- SER_STROBE_OFF;
-}
-
-#endif // AVR_HAS_UART1
-
-
-/**
- * SPI interrupt handler
- */
-SIGNAL(SIG_SPI)
-{
- SER_STROBE_ON;
-
- /* Read incoming byte. */
- if (!fifo_isfull(&ser_spi->rxfifo))
- fifo_push(&ser_spi->rxfifo, SPDR);
- /*
- * FIXME
- else
- ser_spi->status |= SERRF_RXFIFOOVERRUN;
- */
-
- /* Send */
- if (!fifo_isempty(&ser_spi->txfifo))
- SPDR = fifo_pop(&ser_spi->txfifo);
- else
- UARTDescs[SER_SPI].sending = false;
-
- SER_STROBE_OFF;
-}
projects / bertos.git / commitdiff